Merge branch 'main' into rv64im

bench/tests/op/addiw.s

@@ -1,4 +1,4 @@
-# expected: 0000000000000000, FFFFFFFFFFFFFFFF, 0000000000000010
+# expected: 0000000000000000, FFFFFFFFFFFFFFFF, 0000000000000010, 0000000000000000
     .text
 _start:
     # This test CANNOT use li as it uses addiw under the hood
@@ -12,3 +12,10 @@ _start:
     # simple addition
     addi x1, x0, 8
     addiw x31, x1, 8
+
+    # 32bits trim
+    lui x1, 0xFFFFF
+    slli x1, x1, 20
+    addiw x31, x1, 0
+
+

bench/tests/op/addw.s

@@ -0,0 +1,19 @@
+# expected: 0000000000000000, FFFFFFFFFFFFFFFF, 0000000000000010, 0000000000000000
+    .text
+_start:
+    # 0 addition
+    li x1, 0
+    addw x31, x0, x1
+
+    # all bits addition + sign extension to 32 bits then 64 bits
+    li x1, 0x00000000FFFFFFFF
+    addw x31, x0, x1
+
+    # simple addition
+    li x1, 8
+    li x2, 8
+    addw x31, x1, x2
+
+    # 32bits trim
+    li x1, 0xFFFFFFFF00000000
+    addw x31, x0, x1

bench/tests/op/jalr.s

@@ -13,3 +13,4 @@ step2:
     jalr x0, 4(x2) # return to step1, but 1 further
 finish:
     nop
+    addi x31, x0, 0x0AB # This instruction should never be executed

bench/tests/op/ld.s

@@ -0,0 +1,7 @@
+# expected: 1023456789ABCDEF
+    .text
+_start:
+    li x1, 0x1023456789ABCDEF
+    sd x1, 100(x0)
+
+    ld x31, 100(x0)

bench/tests/op/lw.s

@@ -1,7 +1,11 @@
-# expected: 123451BC
+# expected: 123451BC, FFFFFFFFF0000000
     .text
 _start:
     lui x1, 0x12345
     ori x1, x1, 0x1BC
     sw x1, 100(x0)
     lw x31, 100(x0)
+
+    li x1, 0x00000000F0000000
+    sw x1, 100(x0)
+    lw x31, 100(x0)

bench/tests/op/lwu.s

@@ -0,0 +1,6 @@
+# expected: 00000000FFFFFFFF 
+    .text
+_start:
+    li x1, 0xFFFFFFFFFFFFFFFF
+    sw x1, 100(x0)
+    lwu x31, 100(x0)

bench/tests/op/sd.s

@@ -0,0 +1,9 @@
+# expected: 000000009ABCDEF0, 0000000012345678
+    .text
+_start:
+    li x1, 0x123456789ABCDEF0
+    sd x1, 128(x0)
+
+    lwu x31, 128(x0)
+    lwu x31, 132(x0)
+

bench/tests/op/slliw.s

@@ -0,0 +1,10 @@
+# expected: 0000000000000000, FFFFFFFF80000000
+    .text
+_start:
+    # Shift out of 32bits
+    li x1, 0x0000000080000000
+    slliw x31, x1, 1
+
+    # Test sign extension
+    li x1, 0x0000000040000000
+    slliw x31, x1, 1

bench/tests/op/sllw.s

@@ -0,0 +1,16 @@
+# expected: 0000000000000000, FFFFFFFF80000000, 0000000000000000
+    .text
+_start:
+    # Shift out of 32bits
+    li x1, 0x0000000080000000
+    li x2, 1
+    sllw x31, x1, x2
+
+    # Test sign extension
+    li x1, 0x0000000040000000
+    li x2, 1
+    sllw x31, x1, x2
+
+    li x1, 1
+    li x2, 33
+    sllw x31, x1, x2

bench/tests/op/sraiw.s

@@ -0,0 +1,22 @@
+# expected: 0000000000000000, 000000003FFFFFFF, FFFFFFFFC0000000, FFFFFFFFFFFFFFFF, FFFFFFFFFFFFFFFF
+    .text
+_start:
+    # Test 1:  1 >> 1  => 0
+    li    x1, 1
+    sraiw x31, x1, 1   # x31 = 0
+
+    # Test 2:  0x7fffffff >> 1  => 0x3fffffff
+    li    x1, 0x7fffffff
+    sraiw x31, x1, 1   # x31 = 0x000000003fffffff
+
+    # Test 3:  0x80000000 >> 1  => 0xc0000000 (sign-extended)
+    li    x1, 0x80000000
+    sraiw x31, x1, 1   # x31 = 0xffffffffc0000000
+
+    # Test 4:  0x80000000 >> 31 => 0xffffffff (-1)
+    li    x1, 0x80000000
+    sraiw x31, x1, 31  # x31 = 0xffffffffffffffff
+
+    # Test 5:  0xffffffff >> 31 => 0xffffffff (-1)
+    li    x1, -1
+    sraiw x31, x1, 31  # x31 = 0xffffffffffffffff

bench/tests/op/sraw.s

@@ -0,0 +1,27 @@
+# expected: 0000000000000000, 000000003FFFFFFF, FFFFFFFFC0000000, FFFFFFFFFFFFFFFF, FFFFFFFFFFFFFFFF
+    .text
+_start:
+    # Test 1:  1 >> 1  => 0
+    li    x1, 1
+    li x2, 1
+    sraw x31, x1, x2   # x31 = 0
+
+    # Test 2:  0x7fffffff >> 1  => 0x3fffffff
+    li    x1, 0x7fffffff
+    li x2, 1
+    sraw x31, x1, x2   # x31 = 0x000000003fffffff
+
+    # Test 3:  0x80000000 >> 1  => 0xc0000000 (sign-extended)
+    li    x1, 0x80000000
+    li x2, 1
+    sraw x31, x1, x2   # x31 = 0xffffffffc0000000
+
+    # Test 4:  0x80000000 >> 31 => 0xffffffff (-1)
+    li    x1, 0x80000000
+    li x2, 31
+    sraw x31, x1, x2  # x31 = 0xffffffffffffffff
+
+    # Test 5:  0xffffffff >> 31 => 0xffffffff (-1)
+    li    x1, -1
+    li x2, 31
+    sraw x31, x1, x2  # x31 = 0xffffffffffffffff

bench/tests/op/srliw.s

@@ -0,0 +1,14 @@
+# expected: 0000000000000000, 000000003fffffff, 0000000040000000
+    .text
+_start:
+    # Test 1:  1 >> 1  => 0
+    li    x1, 1
+    srliw x31, x1, 1   # x31 = 0
+
+    # Test 2:  0x7fffffff >> 1  => 0x3fffffff
+    li    x1, 0x7fffffff
+    srliw x31, x1, 1   # x31 = 0x000000003fffffff
+
+    # Test 3:  0x80000000 >> 1  => 0x40000000 (not sign-extended)
+    li    x1, 0x80000000
+    srliw x31, x1, 1   # x31 = 0xffffffffc0000000

bench/tests/op/srlw.s

@@ -0,0 +1,22 @@
+# expected: 0000000000000000, 000000003fffffff, 0000000040000000, 0000000000000000
+    .text
+_start:
+    # Test 1:  1 >> 1  => 0
+    li    x1, 1
+    li    x2, 1
+    srlw x31, x1, x2   # x31 = 0
+
+    # Test 2:  0x7fffffff >> 1  => 0x3fffffff
+    li    x1, 0x7fffffff
+    li x2, 1
+    srlw x31, x1, x2   # x31 = 0x000000003fffffff
+
+    # Test 3:  0x80000000 >> 1  => 0x40000000 (not sign-extended)
+    li    x1, 0x80000000
+    li x2, 1
+    srlw x31, x1, x2   # x31 = 0xffffffffc0000000
+
+    li x1, 0x40000000
+    li x2, 33
+    srlw x31, x1, x2
+

bench/tests/op/subw.s

@@ -0,0 +1,19 @@
+# expected: 0000000000000000, FFFFFFFFFFFFFFFF, 0000000000000004, 0000000000000000
+    .text
+_start:
+    # 0 sub
+    li x1, 0
+    subw x31, x0, x1
+
+    # all bits sub + sign extension to 32 bits then 64 bits
+    li x1, 1
+    subw x31, x0, x1
+
+    # simple subtraction
+    li x1, 8
+    li x2, 4
+    subw x31, x1, x2
+
+    # 32bits trim
+    li x1, 0xFFFFFFFF00000000
+    subw x31, x1, x1