Refactor Spec files
This commit is contained in:
@@ -5,11 +5,12 @@ import org.scalatest.freespec.AnyFreeSpec
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import org.scalatest.matchers.must.Matchers
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import java.nio.file.{Files, Paths}
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import scala.jdk.CollectionConverters._
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import scala.io.Source
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import scala.collection.mutable.ListBuffer
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import java.nio.file.FileSystems
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import java.nio.file.Path
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import org.scalatest.ParallelTestExecution
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import projet.ZzTopCommon.expectedValuesFromAsm
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import projet.ZzTopCommon.expectNextValue
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class ZzTopAllSpec
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extends AnyFreeSpec
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@@ -17,60 +18,6 @@ class ZzTopAllSpec
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with ParallelTestExecution
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with ChiselSim {
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def expectedValuesFromAsm(path: String): Seq[BigInt] = {
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val line =
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Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
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line match {
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case Some(l) =>
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l.stripPrefix("# expected:")
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.split(",")
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.map(_.trim)
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.filter(_.nonEmpty)
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.map(str => BigInt(str, 16))
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.toSeq
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case None =>
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Seq.empty
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}
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}
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def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
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val prefix = s"🛑 $msg\n"
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val traceStr =
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if (trace.nonEmpty)
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"Trace:\n" + trace.map(" - " + _).mkString("\n") + "\n"
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else ""
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fail(prefix + traceStr)
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}
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def expectNextValue(
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dut: ZzTop,
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expected: BigInt,
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timeout: Int,
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trace: ListBuffer[String]
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): Unit = {
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var cycles = 0
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val clock_per_cpucycle = 2;
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dut.clock.step(
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clock_per_cpucycle
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) // Attente d'un cycle proc (clock_per_cpu cycles systeme)
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// Attendre une écriture dans x31
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while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
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dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
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cycles += 1
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trace += f"Attente $cycles cycles"
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}
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if (cycles < timeout) {
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// Vérifier la nouvelle valeur
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val got = dut.io.x31.get.peek().litValue
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trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
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if (got != expected) failTrace("Mauvaise sortie", trace)
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} else {
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trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
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failTrace("Simulation bloquée", trace)
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}
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}
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// Fonction de test commune
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def testWith(file: String): Unit = {
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val path = file.replace("/mem/", "/").replace(".mem", ".s")
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@@ -92,10 +39,6 @@ class ZzTopAllSpec
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val dir =
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FileSystems.getDefault().getPath(sys.env("PROOT") + "/bench/mem/tests")
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// val suffix = ".mem"
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// val path = dir + name + suffix
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// print(path)
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var tests = Files
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.walk(dir)
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62
src/test/scala/projet/ZzTopCommon.scala
Normal file
62
src/test/scala/projet/ZzTopCommon.scala
Normal file
@@ -0,0 +1,62 @@
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package projet
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import scala.io.Source
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import scala.collection.mutable.ListBuffer
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import org.scalatest.freespec.AnyFreeSpec
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import chisel3.simulator.scalatest.ChiselSim
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object ZzTopCommon extends AnyFreeSpec with ChiselSim {
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def expectedValuesFromAsm(path: String): Seq[BigInt] = {
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val line =
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Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
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line match {
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case Some(l) =>
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l.stripPrefix("# expected:")
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.split(",")
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.map(_.trim)
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.filter(_.nonEmpty)
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.map(str => BigInt(str, 16))
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.toSeq
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case None =>
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Seq.empty
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}
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}
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def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
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val prefix = s"🛑 $msg\n"
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val traceStr =
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if (trace.nonEmpty)
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"Trace:\n" + trace.map(" - " + _).mkString("\n") + "\n"
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else ""
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fail(prefix + traceStr)
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}
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def expectNextValue(
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dut: ZzTop,
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expected: BigInt,
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timeout: Int,
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trace: ListBuffer[String]
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): Unit = {
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var cycles = 0
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val clock_per_cpucycle = 2;
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dut.clock.step(
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clock_per_cpucycle
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) // Attente d'un cycle proc (clock_per_cpucycle cycles systeme)
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// Attendre une écriture dans x31
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while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
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dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
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cycles += 1
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trace += f"Attente $cycles cycles"
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}
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if (cycles < timeout) {
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// Vérifier la nouvelle valeur
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val got = dut.io.x31.get.peek().litValue
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trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
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if (got != expected) failTrace("Mauvaise sortie", trace)
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} else {
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trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
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failTrace("Simulation bloquée", trace)
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}
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}
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}
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@@ -6,65 +6,11 @@ import org.scalatest.matchers.must.Matchers
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import org.scalatest.prop.TableDrivenPropertyChecks._
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import java.nio.file.{Files, Paths}
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import scala.jdk.CollectionConverters._
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import scala.io.Source
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import scala.collection.mutable.ListBuffer
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import projet.ZzTopCommon.expectedValuesFromAsm
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import projet.ZzTopCommon.expectNextValue
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class ZzTopSpec extends AnyFreeSpec with Matchers with ChiselSim {
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def expectedValuesFromAsm(path: String): Seq[BigInt] = {
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val line =
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Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
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line match {
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case Some(l) =>
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l.stripPrefix("# expected:")
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.split(",")
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.map(_.trim)
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.filter(_.nonEmpty)
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.map(str => BigInt(str, 16))
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.toSeq
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case None =>
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Seq.empty
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}
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}
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def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
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val prefix = s"🛑 $msg\n"
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val traceStr =
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if (trace.nonEmpty)
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"Trace:\n" + trace.map(" - " + _).mkString("\n") + "\n"
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else ""
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fail(prefix + traceStr)
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}
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def expectNextValue(
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dut: ZzTop,
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expected: BigInt,
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timeout: Int,
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trace: ListBuffer[String]
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): Unit = {
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var cycles = 0
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val clock_per_cpucycle = 2;
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dut.clock.step(
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clock_per_cpucycle
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) // Attente d'un cycle proc (clock_per_cpucycle cycles systeme)
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// Attendre une écriture dans x31
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while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
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dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
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cycles += 1
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trace += f"Attente $cycles cycles"
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}
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if (cycles < timeout) {
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// Vérifier la nouvelle valeur
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val got = dut.io.x31.get.peek().litValue
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trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
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if (got != expected) failTrace("Mauvaise sortie", trace)
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} else {
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trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
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failTrace("Simulation bloquée", trace)
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}
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}
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// Fonction de test commune
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def testWith(file: String): Unit = {
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val path = file.replace("/mem/", "/").replace(".mem", ".s")
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