Stage 10: test not passing

bench/tests/op/sb.s

@@ -0,0 +1,10 @@
+# expected: 00010000
+    .text
+_start:
+    addi x1, x0, 0x1
+    sw x1, 28(x0)
+    nop
+    nop
+    nop
+    nop
+    addi x31, x0, 0x0

common/config.gtkw

@@ -1,63 +1,12 @@
-[*]
-[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
-[*] Mon Nov  3 08:12:34 2025
-[*]
-[dumpfile] "/user/9/.base/mullero/home/cours/FMN/projet/build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd"
-[dumpfile_mtime] "Mon Nov  3 08:11:19 2025"
-[dumpfile_size] 59916
-[savefile] "/user/9/.base/mullero/home/cours/FMN/projet/common/config.gtkw"
 [timestart] 0
-[size] 1920 1080
-[pos] -67 -33
 *-14.058537 52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] TOP.
 [treeopen] TOP.svsimTestbench.
 [treeopen] TOP.svsimTestbench.dut.
 [treeopen] TOP.svsimTestbench.dut.core.
-[sst_width] 278
+@4023
-[signals_width] 142
+^>1 ./spike-dasm
-[sst_expanded] 1
+TOP.svsimTestbench.dut.core.instruction[31:0]
-[sst_vpaned_height] 317
-@200
--Instruction
-@c04023
-^>1 spike-dasm
-TOP.svsimTestbench.dut.core.insn[31:0]
-@29
-(0)TOP.svsimTestbench.dut.core.insn[31:0]
-(1)TOP.svsimTestbench.dut.core.insn[31:0]
-(2)TOP.svsimTestbench.dut.core.insn[31:0]
-(3)TOP.svsimTestbench.dut.core.insn[31:0]
-(4)TOP.svsimTestbench.dut.core.insn[31:0]
-(5)TOP.svsimTestbench.dut.core.insn[31:0]
-(6)TOP.svsimTestbench.dut.core.insn[31:0]
-(7)TOP.svsimTestbench.dut.core.insn[31:0]
-(8)TOP.svsimTestbench.dut.core.insn[31:0]
-(9)TOP.svsimTestbench.dut.core.insn[31:0]
-(10)TOP.svsimTestbench.dut.core.insn[31:0]
-(11)TOP.svsimTestbench.dut.core.insn[31:0]
-(12)TOP.svsimTestbench.dut.core.insn[31:0]
-(13)TOP.svsimTestbench.dut.core.insn[31:0]
-(14)TOP.svsimTestbench.dut.core.insn[31:0]
-(15)TOP.svsimTestbench.dut.core.insn[31:0]
-(16)TOP.svsimTestbench.dut.core.insn[31:0]
-(17)TOP.svsimTestbench.dut.core.insn[31:0]
-(18)TOP.svsimTestbench.dut.core.insn[31:0]
-(19)TOP.svsimTestbench.dut.core.insn[31:0]
-(20)TOP.svsimTestbench.dut.core.insn[31:0]
-(21)TOP.svsimTestbench.dut.core.insn[31:0]
-(22)TOP.svsimTestbench.dut.core.insn[31:0]
-(23)TOP.svsimTestbench.dut.core.insn[31:0]
-(24)TOP.svsimTestbench.dut.core.insn[31:0]
-(25)TOP.svsimTestbench.dut.core.insn[31:0]
-(26)TOP.svsimTestbench.dut.core.insn[31:0]
-(27)TOP.svsimTestbench.dut.core.insn[31:0]
-(28)TOP.svsimTestbench.dut.core.insn[31:0]
-(29)TOP.svsimTestbench.dut.core.insn[31:0]
-(30)TOP.svsimTestbench.dut.core.insn[31:0]
-(31)TOP.svsimTestbench.dut.core.insn[31:0]
-@1401201
--group_end
 @22
 TOP.svsimTestbench.dut.core.pc[31:0]
 TOP.svsimTestbench.dut.core.rd[4:0]
@@ -72,5 +21,3 @@ TOP.svsimTestbench.dut.io_x31[31:0]
 @28
 TOP.svsimTestbench.dut.io_valid_x31
 TOP.svsimTestbench.dut.core.rdValid
-[pattern_trace] 1
-[pattern_trace] 0

src/main/scala/projet/ControlUnit.scala

@@ -17,9 +17,9 @@ class CUInterface extends Bundle {
     val is_jump = Output(Bool())
 
     // DMem connections
-    val memory_size = Input(DMemSize())
+    val memory_size = Output(DMemSize())
-    val memory_en = Input(Bool())
+    val memory_en = Output(Bool())
-    val memory_we = Input(Bool())
+    val memory_we = Output(Bool())
 
     // Muxers
     // The naming convention is as follows : mux_xxx_yyy.

src/main/scala/projet/DMem.scala

@@ -33,8 +33,8 @@ class DMem extends Module {
                     (io.addr(1) * 8.U)
             }
             is(DMemSize.Half) {
-                bytes_enabled(io.addr(1) * 2.U(2.W)) := true.B
+                bytes_enabled((io.addr(1) * 2.U(2.W))(1, 0)) := true.B
-                bytes_enabled(io.addr(1) * 2.U(2.W) + 1.U(2.W)) := true.B
+                bytes_enabled((io.addr(1) * 2.U(2.W) + 1.U(2.W))(1, 0)) := true.B
                 data := io.data_in << (io.addr(1) * 16.U)
             }
             is(DMemSize.Word) {
@@ -47,4 +47,6 @@ class DMem extends Module {
     io.dbus.be := bytes_enabled
 
     io.dbus.wdata := data
+
+    io.data_out := 0.U
 }

src/main/scala/projet/IDMem.scala

@@ -48,6 +48,8 @@ class dpram( // nom identique à celui du verilog
         val doutB = Output(UInt(DATA_WIDTH.W))
         val dinB = Input(UInt(DATA_WIDTH.W))
         val weB = Input(UInt(NUM_COL.W))
+
+        val ram_block = Output(UInt(DATA_WIDTH.W))
     })
 }
 
@@ -134,6 +136,8 @@ class IDMem(sim: Boolean, addrWidth: Int, memFile: String = "") extends Module {
             )
         )
 
+        dontTouch(unifiedRam.io.ram_block)
+
         unifiedRam.io.clkA := io.clki
         unifiedRam.io.clkB := io.clkd
         // instructions sur le port a