Stage 10: test not passing

src/main/scala/projet/ControlUnit.scala

@@ -17,9 +17,9 @@ class CUInterface extends Bundle {
     val is_jump = Output(Bool())
 
     // DMem connections
-    val memory_size = Input(DMemSize())
-    val memory_en = Input(Bool())
-    val memory_we = Input(Bool())
+    val memory_size = Output(DMemSize())
+    val memory_en = Output(Bool())
+    val memory_we = Output(Bool())
 
     // Muxers
     // The naming convention is as follows : mux_xxx_yyy.

src/main/scala/projet/DMem.scala

@@ -33,8 +33,8 @@ class DMem extends Module {
                     (io.addr(1) * 8.U)
             }
             is(DMemSize.Half) {
-                bytes_enabled(io.addr(1) * 2.U(2.W)) := true.B
-                bytes_enabled(io.addr(1) * 2.U(2.W) + 1.U(2.W)) := true.B
+                bytes_enabled((io.addr(1) * 2.U(2.W))(1, 0)) := true.B
+                bytes_enabled((io.addr(1) * 2.U(2.W) + 1.U(2.W))(1, 0)) := true.B
                 data := io.data_in << (io.addr(1) * 16.U)
             }
             is(DMemSize.Word) {
@@ -47,4 +47,6 @@ class DMem extends Module {
     io.dbus.be := bytes_enabled
 
     io.dbus.wdata := data
+
+    io.data_out := 0.U
 }

src/main/scala/projet/IDMem.scala

@@ -48,6 +48,8 @@ class dpram( // nom identique à celui du verilog
         val doutB = Output(UInt(DATA_WIDTH.W))
         val dinB = Input(UInt(DATA_WIDTH.W))
         val weB = Input(UInt(NUM_COL.W))
+
+        val ram_block = Output(UInt(DATA_WIDTH.W))
     })
 }
 
@@ -134,6 +136,8 @@ class IDMem(sim: Boolean, addrWidth: Int, memFile: String = "") extends Module {
             )
         )
 
+        dontTouch(unifiedRam.io.ram_block)
+
         unifiedRam.io.clkA := io.clki
         unifiedRam.io.clkB := io.clkd
         // instructions sur le port a