Stage 11: Passing tests

src/main/scala/projet/ControlUnit.scala

@@ -20,6 +20,9 @@ class CUInterface extends Bundle {
     val memory_size = Output(DMemSize())
     val memory_en = Output(Bool())
     val memory_we = Output(Bool())
+    val memory_sign_extend = Output(
+        Bool()
+    ) // Wether to signe extend the output of the memory for bytes, half loads
 
     // Muxers
     // The naming convention is as follows : mux_xxx_yyy.
@@ -45,6 +48,9 @@ class CUInterface extends Bundle {
 
     // Selects pc or write back for register write
     val mux_writeback_pc = Output(Bool())
+
+    // Selects aluout or memory data out for writeback_line
+    val mux_executeout_dout = Output(Bool())
 }
 
 object OpType extends ChiselEnum {
@@ -101,6 +107,7 @@ class ControlUnit() extends Module {
     io.memory_size := DMemSize.Word
     io.memory_en := false.B
     io.memory_we := false.B
+    io.memory_sign_extend := false.B;
     io.mux_alu_imm := true.B;
     io.mux_rega_pc := true.B;
     io.mux_regb_imm := true.B;
@@ -108,6 +115,7 @@ class ControlUnit() extends Module {
     io.mux_regpc_executepc := true.B;
     io.mux_writeback_pc := true.B;
     io.mux_pcadder_writeback := true.B;
+    io.mux_executeout_dout := true.B;
 
     // Decode instruction
     val opcode = io.instruction(6, 0);
@@ -447,21 +455,39 @@ class ControlUnit() extends Module {
             val LB = "b000".U
             val LH = "b001".U
             val LW = "b010".U
+            val LBU = "b100".U
+            val LHU = "b101".U
         }
 
         io.alu_opcode := AluOpCode.Add
         io.mux_alu_imm := true.B
         io.mux_rega_pc := true.B
         io.mux_regb_imm := false.B
+        io.mux_writeback_pc := true.B;
+        io.mux_executeout_dout := false.B;
         io.reg_file_we := true.B
         io.memory_en := true.B
+        io.memory_we := false.B
         switch(funct3) {
+            // Byte load
             is(Funct3.LB) {
                 io.memory_size := DMemSize.Byte
+                io.memory_sign_extend := true.B;
             }
+            is(Funct3.LBU) {
+                io.memory_size := DMemSize.Byte
+            }
+
+            // Half load
             is(Funct3.LH) {
                 io.memory_size := DMemSize.Half
+                io.memory_sign_extend := true.B;
             }
+            is(Funct3.LHU) {
+                io.memory_size := DMemSize.Half
+            }
+
+            // Word load
             is(Funct3.LW) {
                 io.memory_size := DMemSize.Word
             }