Stage 4: Implements auipc

src/main/scala/projet/Rv32i.scala

@@ -13,22 +13,30 @@ class Rv32i(sim: Boolean = true) extends Module {
 
     val reg_pc = RegInit(0.U(32.W));
     val reg_file = Module(new RegFile(sim));
+    val instruction = io.ibus.rdata;
+
     reg_file.io.rd_data := 0.U;
     io.x31 := reg_file.io.x31
     if (sim) {
         io.valid_x31.get := reg_file.io.valid_x31.get
     }
+
+    val alu = Module(new Alu());
     val control_unit = Module(new ControlUnit());
+
+    alu.io.opcode := control_unit.io.alu_opcode;
     reg_file.io.we := control_unit.io.reg_file_we
 
     // Increment PC each clock
     reg_pc := reg_pc + 4.U;
 
+    // PC delayed to execute stage for auipc op
+    val execute_pc = Delay.Delay(reg_pc, 1, 0.U);
+
     // Fetch instruction
     io.ibus.en := true.B;
     io.ibus.addr := reg_pc;
 
-    val instruction = io.ibus.rdata;
     control_unit.io.instruction := instruction;
 
     // Decode rs1 index
@@ -42,11 +50,15 @@ class Rv32i(sim: Boolean = true) extends Module {
     reg_file.io.rd_addr := rd
 
     // Decode imm-u
-    val imm_u = instruction(31, 12)
+    val imm_u = Cat(instruction(31, 12), 0.U(12.W));
 
-    // Send imm-u to the register file
-    reg_file.io.rd_data := Cat(imm_u, 0.U(12.W))
+    // EXECUTE
+    
+    alu.io.a := execute_pc;
+    alu.io.b := imm_u;
 
+    reg_file.io.rd_data := Mux(control_unit.io.mux_imm_alu, alu.io.out, imm_u);
+  
     io.dbus.addr := 0.U;
     io.dbus.wdata := 0.U;
     io.dbus.be := VecInit(false.B, false.B, false.B, false.B)