Stage 4: Implements auipc

src/main/scala/projet/RegFile.scala

@@ -24,21 +24,26 @@ class RegFile(sim: Boolean = false) extends Module {
         }
     }
 
-    val valid = WireInit(false.B);
     when(io.we && io.rd_addr =/= 0.U) {
-        regs(io.rd_addr) := io.rd_data
+      regs(io.rd_addr) := io.rd_data
+    }
 
-        if (sim) {
-            when(io.rd_addr === 31.U) {
-                valid := true.B
-            }
-        }
-    }
-    if (sim) {
-        io.valid_x31.get := Delay.Delay(valid, 2, false.B)
-    }
     io.rs1_data := regs(io.rs1_addr)
     io.rs2_data := regs(io.rs2_addr)
 
-    io.x31 := regs(31)
+    // Simulation stuff
+    val valid = WireInit(false.B);
+    when(io.we && io.rd_addr === 31.U)
+    {
+      io.x31 := io.rd_data  
+      if (sim) {
+          valid := true.B
+      }
+    }.otherwise
+    {
+      io.x31 := regs(31)
+    }
+    if (sim) {
+      io.valid_x31.get := Delay.Delay(valid, 1, false.B)
+    }
 }