Stage 4: Implements auipc

src/main/scala/projet/ControlUnit.scala

@@ -7,10 +7,14 @@ import chisel3.util.is
 class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
     val reg_file_we = Output(Bool())
+    val alu_opcode = Output(AluOpCode())
+
+    val mux_imm_alu = Output(Bool())
 }
 
 object OPCode extends ChiselEnum {
     val LUI = 0b0110111.U
+    val AUIPC = 0b0010111.U
 }
 
 class ControlUnit() extends Module {
@@ -19,9 +23,17 @@ class ControlUnit() extends Module {
     val io = IO(new CUInterface())
 
     io.reg_file_we := false.B
+    io.alu_opcode := AluOpCode.Add
+    io.mux_imm_alu := false.B;
     switch(io.instruction(6, 0)) {
         is(LUI) {
             io.reg_file_we := true.B
+            io.mux_imm_alu := false.B;
+        }
+        is(AUIPC) {
+            io.alu_opcode := AluOpCode.Add 
+            io.reg_file_we := true.B
+            io.mux_imm_alu := true.B;
         }
     }
 }