Stage 4: Implements auipc

This commit is contained in:
2025-11-05 18:40:27 +01:00
parent 3870e05613
commit 5df85799ef
5 changed files with 83 additions and 16 deletions

View File

@@ -0,0 +1,32 @@
package projet
import chisel3._
import chisel3.util.switch
import chisel3.util.is
object AluOpCode extends ChiselEnum
{
val Add = Value
}
class Alu extends Module {
import AluOpCode._
val io = IO(new Bundle {
val a = Input(UInt(32.W))
val b = Input(UInt(32.W))
val out = Output(UInt(32.W))
val opcode = Input(AluOpCode())
})
io.out := 0.U;
switch(io.opcode)
{
is(Add)
{
io.out := io.a + io.b;
}
}
}