Stage 12: passing tests

src/main/scala/projet/Rv32i.scala

@@ -82,43 +82,48 @@ class Rv32i(sim: Boolean = true) extends Module {
     reg_rd_index := rd_index;
     reg_file.io.rd_addr := reg_rd_index;
 
+    val writeback_line = Mux(
+        reg_mux_executeout_dout,
+        reg_execute_out,
+        dmem.io.data_out
+    );
+    val rs1_data =
+        Mux(rs1_index === reg_rd_index && rs1_index =/= 0.U, writeback_line, reg_file.io.rs1_data)
+    val rs2_data =
+        Mux(rs2_index === reg_rd_index && rs2_index =/= 0.U, writeback_line, reg_file.io.rs2_data)
+
     // EXECUTE
 
     val imm = immediate_decoder.io.immediate
 
     alu.io.a := Mux(
         control_unit.io.mux_rega_pc,
-        reg_file.io.rs1_data,
+        rs1_data,
         execute_pc
     );
-    alu.io.b := Mux(control_unit.io.mux_regb_imm, reg_file.io.rs2_data, imm);
+    alu.io.b := Mux(control_unit.io.mux_regb_imm, rs2_data, imm);
 
     // Select what to send on writeback line
     val execute_out = Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);
     reg_execute_out := execute_out;
 
     reg_mux_executeout_dout := control_unit.io.mux_executeout_dout;
-    val writeback_line = Mux(
-        reg_mux_executeout_dout,
-        reg_execute_out,
-        dmem.io.data_out
-    );
 
     reg_file.io.rd_data :=
         Mux(
             Delay.Delay(control_unit.io.mux_writeback_pc, 1, true.B),
             writeback_line,
-            reg_pc
+            Delay.Delay(reg_pc, 1, 0.U)
         );
 
     // Writeback pipelining registers
     reg_pc := Mux(
-        control_unit.io.mux_pcadder_writeback,
+        Delay.Delay(control_unit.io.mux_pcadder_writeback, 1, true.B),
         pc_adder_out,
         writeback_line
     );
 
-    dmem.io.data_in := reg_file.io.rs2_data
+    dmem.io.data_in := rs2_data
     dmem.io.addr := execute_out
 
     io.ibus.wdata := 0.U;