Stage 10: not tested

src/main/scala/projet/ControlUnit.scala

@@ -16,6 +16,11 @@ class CUInterface extends Bundle {
     // True if the decoded instruction is a jump
     val is_jump = Output(Bool())
 
+    // DMem connections
+    val memory_size = Input(DMemSize())
+    val memory_en = Input(Bool())
+    val memory_we = Input(Bool())
+
     // Muxers
     // The naming convention is as follows : mux_xxx_yyy.
     // If the signal is hot, xxx is selected otherwise yyy is selected
@@ -43,7 +48,7 @@ class CUInterface extends Bundle {
 }
 
 object OpType extends ChiselEnum {
-    val U, I, IR, J, B = Value
+    val U, I, IR, J, B, S = Value
 }
 
 object OpCode extends ChiselEnum {
@@ -78,6 +83,9 @@ object OpCode extends ChiselEnum {
 
     // Type B
     val OpBranch = "b1100011".U
+
+    // Type S
+    val OpStore = "b0100011".U
 }
 
 class ControlUnit() extends Module {
@@ -87,6 +95,9 @@ class ControlUnit() extends Module {
     io.alu_opcode := AluOpCode.Add
     io.optype := OpType.U
     io.is_jump := false.B;
+    io.memory_size := DMemSize.Word
+    io.memory_en := false.B
+    io.memory_we := false.B
     io.mux_alu_imm := true.B;
     io.mux_rega_pc := true.B;
     io.mux_regb_imm := true.B;
@@ -164,6 +175,11 @@ class ControlUnit() extends Module {
             io.optype := OpType.B;
             opBranch(funct3, io);
         }
+
+        is(OpCode.OpStore) {
+            io.optype := OpType.S
+            opStore(funct3, io);
+        }
     }
 
     // Implements functions for all instruction of the opImm kind
@@ -389,4 +405,30 @@ class ControlUnit() extends Module {
             io.is_jump := true.B;
         }
     }
+    // Implements functions for all instruction of the OpStore kind
+    def opStore(funct3: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpStore instruction
+        object Funct3 extends ChiselEnum {
+            val SB = "b000".U
+            val SH = "b001".U
+            val SW = "b010".U
+        }
+
+        io.alu_opcode := AluOpCode.Add
+        io.mux_alu_imm := true.B
+        io.mux_rega_pc := true.B
+        io.mux_regb_imm := false.B
+        io.memory_we := true.B
+        switch(funct3) {
+            is(Funct3.SB) {
+                io.memory_size := DMemSize.Byte
+            }
+            is(Funct3.SH) {
+                io.memory_size := DMemSize.Half
+            }
+            is(Funct3.SW) {
+                io.memory_size := DMemSize.Word
+            }
+        }
+    }
 }