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This commit is contained in:
Julien THILLARD
2025-11-04 18:08:45 +01:00
parent fa60ce372f
commit 41c5da1a64
13 changed files with 664 additions and 593 deletions
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79
src/main/scala/projet/Rv32i.scala
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@@ -3,54 +3,53 @@ package projet
import chisel3._
class Rv32i(sim: Boolean = true) extends Module {
val io = IO(new Bundle {
val ibus = Flipped(new BusInterface)
val dbus = Flipped(new BusInterface)
val x31 = Output(UInt(32.W))
val valid_x31 = if (sim) Some(Output(Bool())) else None
})
val io = IO(new Bundle {
val ibus = Flipped(new BusInterface)
val dbus = Flipped(new BusInterface)
val x31 = Output(UInt(32.W))
val valid_x31 = if (sim) Some(Output(Bool())) else None
})
val reg_pc = RegInit(0.U(32.W));
val reg_file = Module(new RegFile(sim));
reg_file.io.rd_data := 0.U;
reg_file.io.we := 0.U;
val reg_pc = RegInit(0.U(32.W));
val reg_file = Module(new RegFile(sim));
reg_file.io.rd_data := 0.U;
reg_file.io.we := 0.U;
// Increment PC each clock
reg_pc := reg_pc + 4.U;
// Increment PC each clock
reg_pc := reg_pc + 4.U;
// Fetch instruction
io.ibus.en := true.B;
io.ibus.addr := reg_pc;
// Fetch instruction
io.ibus.en := true.B;
io.ibus.addr := reg_pc;
val insn = io.ibus.rdata;
val insn = io.ibus.rdata;
// Decode rs1 index
val rs1 = insn(19, 15)
reg_file.io.rs1_addr := rs1
// Decode rs2 index
val rs2 = insn(24, 20)
reg_file.io.rs2_addr := rs2
// Decode rd index
val rd = insn(11, 7)
reg_file.io.rd_addr := rd
// Decode rs1 index
val rs1 = insn(19, 15)
reg_file.io.rs1_addr := rs1
// Decode rs2 index
val rs2 = insn(24, 20)
reg_file.io.rs2_addr := rs2
// Decode rd index
val rd = insn(11, 7)
reg_file.io.rd_addr := rd
// Decode imm-u
val imm_u = insn(31, 12)
// Decode imm-u
val imm_u = insn(31, 12)
// Debug instruction
io.x31 := reg_file.io.rs1_data;
if(sim)
{
io.valid_x31.get := true.B;
}
// Debug instruction
io.x31 := reg_file.io.rs1_data;
if (sim) {
io.valid_x31.get := true.B;
}
io.dbus.addr := 0.U;
io.dbus.wdata := 0.U;
io.dbus.be := VecInit(false.B,false.B,false.B,false.B)
io.dbus.en := false.B;
io.dbus.addr := 0.U;
io.dbus.wdata := 0.U;
io.dbus.be := VecInit(false.B, false.B, false.B, false.B)
io.dbus.en := false.B;
io.ibus.wdata := 0.U;
io.ibus.be := VecInit(false.B,false.B,false.B,false.B)
io.ibus.wdata := 0.U;
io.ibus.be := VecInit(false.B, false.B, false.B, false.B)
//locally(sim)
// locally(sim)
}