Stage 10: passing tests

src/main/scala/projet/ControlUnit.scala

@@ -86,6 +86,9 @@ object OpCode extends ChiselEnum {
 
     // Type S
     val OpStore = "b0100011".U
+
+    // Type I
+    val OpLoad = "b0000011".U
 }
 
 class ControlUnit() extends Module {
@@ -180,6 +183,11 @@ class ControlUnit() extends Module {
             io.optype := OpType.S
             opStore(funct3, io);
         }
+
+        is(OpCode.OpLoad) {
+            io.optype := OpType.I
+            opLoad(funct3, io);
+        }
     }
 
     // Implements functions for all instruction of the opImm kind
@@ -419,6 +427,7 @@ class ControlUnit() extends Module {
         io.mux_rega_pc := true.B
         io.mux_regb_imm := false.B
         io.memory_we := true.B
+        io.memory_en := true.B
         switch(funct3) {
             is(Funct3.SB) {
                 io.memory_size := DMemSize.Byte
@@ -431,4 +440,31 @@ class ControlUnit() extends Module {
             }
         }
     }
+    // Implements functions for all instruction of the OpLoad kind
+    def opLoad(funct3: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpLoad instruction
+        object Funct3 extends ChiselEnum {
+            val LB = "b000".U
+            val LH = "b001".U
+            val LW = "b010".U
+        }
+
+        io.alu_opcode := AluOpCode.Add
+        io.mux_alu_imm := true.B
+        io.mux_rega_pc := true.B
+        io.mux_regb_imm := false.B
+        io.reg_file_we := true.B
+        io.memory_en := true.B
+        switch(funct3) {
+            is(Funct3.LB) {
+                io.memory_size := DMemSize.Byte
+            }
+            is(Funct3.LH) {
+                io.memory_size := DMemSize.Half
+            }
+            is(Funct3.LW) {
+                io.memory_size := DMemSize.Word
+            }
+        }
+    }
 }