Stage 10: passing tests

src/main/scala/projet/ControlUnit.scala

@@ -86,6 +86,9 @@ object OpCode extends ChiselEnum {
 
     // Type S
     val OpStore = "b0100011".U
+
+    // Type I
+    val OpLoad = "b0000011".U
 }
 
 class ControlUnit() extends Module {
@@ -180,6 +183,11 @@ class ControlUnit() extends Module {
             io.optype := OpType.S
             opStore(funct3, io);
         }
+
+        is(OpCode.OpLoad) {
+            io.optype := OpType.I
+            opLoad(funct3, io);
+        }
     }
 
     // Implements functions for all instruction of the opImm kind
@@ -419,6 +427,7 @@ class ControlUnit() extends Module {
         io.mux_rega_pc := true.B
         io.mux_regb_imm := false.B
         io.memory_we := true.B
+        io.memory_en := true.B
         switch(funct3) {
             is(Funct3.SB) {
                 io.memory_size := DMemSize.Byte
@@ -431,4 +440,31 @@ class ControlUnit() extends Module {
             }
         }
     }
+    // Implements functions for all instruction of the OpLoad kind
+    def opLoad(funct3: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpLoad instruction
+        object Funct3 extends ChiselEnum {
+            val LB = "b000".U
+            val LH = "b001".U
+            val LW = "b010".U
+        }
+
+        io.alu_opcode := AluOpCode.Add
+        io.mux_alu_imm := true.B
+        io.mux_rega_pc := true.B
+        io.mux_regb_imm := false.B
+        io.reg_file_we := true.B
+        io.memory_en := true.B
+        switch(funct3) {
+            is(Funct3.LB) {
+                io.memory_size := DMemSize.Byte
+            }
+            is(Funct3.LH) {
+                io.memory_size := DMemSize.Half
+            }
+            is(Funct3.LW) {
+                io.memory_size := DMemSize.Word
+            }
+        }
+    }
 }

src/main/scala/projet/DMem.scala

@@ -3,6 +3,7 @@ package projet
 import chisel3._
 import chisel3.util.switch
 import chisel3.util.is
+import chisel3.util.Cat
 
 object DMemSize extends ChiselEnum {
     val Byte, Half, Word = Value
@@ -20,21 +21,23 @@ class DMem extends Module {
 
         val data_out = Output(UInt(32.W))
     })
-    io.dbus.addr := io.addr;
+    io.dbus.addr := Cat(io.addr(31, 2), 0.U(2.W));
     io.dbus.en := io.en;
 
     val bytes_enabled = VecInit(false.B, false.B, false.B, false.B)
-    val data = WireInit(0.U)
+    val data = WireInit(0.U(32.W))
+
     when(io.we) {
         switch(io.size) {
             is(DMemSize.Byte) {
                 bytes_enabled(io.addr(1, 0)) := true.B
-                data := (io.data_in << (io.addr(1) * 16.U)) <<
-                    (io.addr(1) * 8.U)
+                data := io.data_in << (io.addr(1) * 16.U + io.addr(0) * 8.U)
             }
             is(DMemSize.Half) {
                 bytes_enabled((io.addr(1) * 2.U(2.W))(1, 0)) := true.B
-                bytes_enabled((io.addr(1) * 2.U(2.W) + 1.U(2.W))(1, 0)) := true.B
+                bytes_enabled(
+                    (io.addr(1) * 2.U(2.W) + 1.U(2.W))(1, 0)
+                ) := true.B
                 data := io.data_in << (io.addr(1) * 16.U)
             }
             is(DMemSize.Word) {

src/main/scala/projet/IDMem.scala

@@ -48,8 +48,6 @@ class dpram( // nom identique à celui du verilog
         val doutB = Output(UInt(DATA_WIDTH.W))
         val dinB = Input(UInt(DATA_WIDTH.W))
         val weB = Input(UInt(NUM_COL.W))
-
-        val ram_block = Output(UInt(DATA_WIDTH.W))
     })
 }
 
@@ -136,8 +134,6 @@ class IDMem(sim: Boolean, addrWidth: Int, memFile: String = "") extends Module {
             )
         )
 
-        dontTouch(unifiedRam.io.ram_block)
-
         unifiedRam.io.clkA := io.clki
         unifiedRam.io.clkB := io.clkd
         // instructions sur le port a

src/main/scala/projet/Rv32i.scala

@@ -95,7 +95,7 @@ class Rv32i(sim: Boolean = true) extends Module {
       writeback_line
       );
 
-    dmem.io.data_in := rs2
+    dmem.io.data_in := reg_file.io.rs2_data
     dmem.io.addr := writeback_line
 
     io.ibus.wdata := 0.U;