Implements stage 3

src/main/scala/projet/Rv32i.scala

@@ -1,6 +1,7 @@
 package projet
 
 import chisel3._
+import chisel3.util.Cat
 
 class Rv32i(sim: Boolean = true) extends Module {
     val io = IO(new Bundle {
@@ -13,7 +14,12 @@ class Rv32i(sim: Boolean = true) extends Module {
     val reg_pc = RegInit(0.U(32.W));
     val reg_file = Module(new RegFile(sim));
     reg_file.io.rd_data := 0.U;
-    reg_file.io.we := 0.U;
+    io.x31 := reg_file.io.x31
+    if (sim) {
+        io.valid_x31.get := reg_file.io.valid_x31.get
+    }
+    val control_unit = Module(new ControlUnit());
+    reg_file.io.we := control_unit.io.reg_file_we
 
     // Increment PC each clock
     reg_pc := reg_pc + 4.U;
@@ -22,26 +28,24 @@ class Rv32i(sim: Boolean = true) extends Module {
     io.ibus.en := true.B;
     io.ibus.addr := reg_pc;
 
-    val insn = io.ibus.rdata;
+    val instruction = io.ibus.rdata;
+    control_unit.io.instruction := instruction;
 
     // Decode rs1 index
-    val rs1 = insn(19, 15)
+    val rs1 = instruction(19, 15)
     reg_file.io.rs1_addr := rs1
     // Decode rs2 index
-    val rs2 = insn(24, 20)
+    val rs2 = instruction(24, 20)
     reg_file.io.rs2_addr := rs2
     // Decode rd index
-    val rd = insn(11, 7)
+    val rd = instruction(11, 7)
     reg_file.io.rd_addr := rd
 
     // Decode imm-u
-    val imm_u = insn(31, 12)
+    val imm_u = instruction(31, 12)
 
-    // Debug instruction
-    io.x31 := reg_file.io.rs1_data;
-    if (sim) {
-        io.valid_x31.get := true.B;
-    }
+    // Send imm-u to the register file
+    reg_file.io.rd_data := Cat(imm_u, 0.U(12.W))
 
     io.dbus.addr := 0.U;
     io.dbus.wdata := 0.U;