Implements stage 3

src/main/scala/projet/RegFile.scala

@@ -11,6 +11,9 @@ class RegFile(sim: Boolean = false) extends Module {
         val we = Input(Bool())
         val rs1_data = Output(UInt(32.W))
         val rs2_data = Output(UInt(32.W))
+
+        val x31 = Output(UInt(32.W))
+        val valid_x31 = if (sim) Some(Output(Bool())) else None
     })
 
     val regs = Mem(32, UInt(32.W))
@@ -21,9 +24,21 @@ class RegFile(sim: Boolean = false) extends Module {
         }
     }
 
+    val valid = WireInit(false.B);
     when(io.we && io.rd_addr =/= 0.U) {
         regs(io.rd_addr) := io.rd_data
+
+        if (sim) {
+            when(io.rd_addr === 31.U) {
+                valid := true.B
+            }
+        }
+    }
+    if (sim) {
+        io.valid_x31.get := Delay.Delay(valid, 2, false.B)
     }
     io.rs1_data := regs(io.rs1_addr)
     io.rs2_data := regs(io.rs2_addr)
+
+    io.x31 := regs(31)
 }