Implements stage 3
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27
src/main/scala/projet/ControlUnit.scala
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27
src/main/scala/projet/ControlUnit.scala
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package projet
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import chisel3._
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import chisel3.util.switch
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import chisel3.util.is
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class CUInterface extends Bundle {
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val instruction = Input(UInt(32.W))
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val reg_file_we = Output(Bool())
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}
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object OPCode extends ChiselEnum {
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val LUI = 0b0110111.U
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}
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class ControlUnit() extends Module {
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import OPCode._
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val io = IO(new CUInterface())
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io.reg_file_we := false.B
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switch(io.instruction(6, 0)) {
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is(LUI) {
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io.reg_file_we := true.B
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}
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}
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}
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