Implements stage 3

This commit is contained in:
2025-11-05 17:23:33 +01:00
parent 41c5da1a64
commit 3870e05613
4 changed files with 73 additions and 11 deletions

View File

@@ -0,0 +1,27 @@
package projet
import chisel3._
import chisel3.util.switch
import chisel3.util.is
class CUInterface extends Bundle {
val instruction = Input(UInt(32.W))
val reg_file_we = Output(Bool())
}
object OPCode extends ChiselEnum {
val LUI = 0b0110111.U
}
class ControlUnit() extends Module {
import OPCode._
val io = IO(new CUInterface())
io.reg_file_we := false.B
switch(io.instruction(6, 0)) {
is(LUI) {
io.reg_file_we := true.B
}
}
}