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patch du Makefile pour les pb de conflits scratch ENsimag

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Olivier Muller
2025-11-04 16:58:14 +01:00
parent cb3dddc77a
commit 35bdeb2fd0
1 changed files with 3 additions and 1 deletions
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4
Makefile
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@@ -97,7 +97,7 @@ mill:
autotest: mill compile ##! Lance la simulation automatique pour tous les tests ou juste celui fourni dans PROG autotest: mill compile ##! Lance la simulation automatique pour tous les tests ou juste celui fourni dans PROG
@PROOT=$(PWD) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) $(FILTRE_TEST) @PROOT=$(PWD) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) $(FILTRE_TEST)
simulation: compile ##! Lance gtkwave sur le test fourni dans PROG simulation: mill compile ##! Lance gtkwave sur le test fourni dans PROG
@$(call check_vars,PROG) @$(call check_vars,PROG)
@PROOT=$(PWD) PROG=$(PROG) CYCLES=$(CYCLES) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) -- -DemitVcd=1 -z "gtkwave" @PROOT=$(PWD) PROG=$(PROG) CYCLES=$(CYCLES) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) -- -DemitVcd=1 -z "gtkwave"
@gtkwave -a common/config.gtkw ./build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd @gtkwave -a common/config.gtkw ./build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd
@@ -182,5 +182,7 @@ fpga: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw ##! Génére le
, " Programmation",prog.log ) , " Programmation",prog.log )
##@ Nettoyage ##@ Nettoyage
TMPREP = /scratch/$(LOGNAME)
clean: ##! Fais le nettoyage clean: ##! Fais le nettoyage
$(call q, rm -rf $(TOCLEAN),) $(call q, rm -rf $(TOCLEAN),)
@if [ -e $(TMPREP) ] && [ ! -d $(TMPREP) ]; then rm -f $(TMPREP) ;fi