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Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa

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Albin Chaboissier
2025-11-13 10:13:53 +01:00
parent 3958a6ad8f d225894765
commit 355c700efe
1 changed files with 10 additions and 8 deletions
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18
src/test/scala/projet/ZzTopCommon.scala
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@@ -7,19 +7,21 @@ import chisel3.simulator.scalatest.ChiselSim
object ZzTopCommon extends AnyFreeSpec with ChiselSim { object ZzTopCommon extends AnyFreeSpec with ChiselSim {
def expectedValuesFromAsm(path: String): Seq[BigInt] = { def expectedValuesFromAsm(path: String): Seq[BigInt] = {
val line = Source
Source.fromFile(path).getLines().find(_.startsWith("# expected:")) .fromFile(path)
line match { .getLines()
case Some(l) => .filter(_.startsWith("# expected:"))
l.stripPrefix("# expected:") .map(
_.stripPrefix("# expected:")
.split(",") .split(",")
.map(_.trim) .map(_.trim)
.filter(_.nonEmpty) .filter(_.nonEmpty)
.map(str => BigInt(str, 16)) .map(str => BigInt(str, 16))
.toSeq .toSeq
case None => )
Seq.empty .fold(Seq.empty)((acc, line) => {
} acc.concat(line)
})
} }
def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = { def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {