Stage 6: implementation, untested

src/main/scala/projet/Alu.scala

@@ -4,29 +4,60 @@ import chisel3._
 import chisel3.util.switch
 import chisel3.util.is
 
-object AluOpCode extends ChiselEnum
-{
-  val Add = Value  
+object AluOpCode extends ChiselEnum {
+    val Add, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
+        LessThanSigned, LessThanUnsigned = Value
 }
 
 class Alu extends Module {
-  import AluOpCode._
+    import AluOpCode._
 
-  val io = IO(new Bundle {
-    val a = Input(UInt(32.W))
-    val b = Input(UInt(32.W))
-    val out = Output(UInt(32.W))
-    val opcode = Input(AluOpCode())
-  })
+    val io = IO(new Bundle {
+        val a = Input(UInt(32.W))
+        val b = Input(UInt(32.W))
+        val out = Output(UInt(32.W))
+        val opcode = Input(AluOpCode())
+    })
 
-  io.out := 0.U;
-  
-  switch(io.opcode)
-  {
-    is(Add)
-    {
-      io.out := io.a + io.b;
+    io.out := 0.U;
+
+    switch(io.opcode) {
+        is(Add) {
+            io.out := io.a + io.b;
+        }
+
+        is(And) {
+            io.out := io.a & io.b;
+        }
+
+        is(Or) {
+            io.out := io.a | io.b;
+        }
+
+        is(Xor) {
+            io.out := io.a ^ io.b;
+        }
+
+        is(ShiftLeft) {
+            io.out := io.a << io.b(4, 0);
+        }
+
+        is(ShiftRight) {
+            io.out := io.a >> io.b(4, 0);
+        }
+
+        is(ShiftArithmeticRight) {
+            // >> means arithmetic shift for SInts
+            io.out := (io.a.asSInt >> io.b(4, 0)).asUInt;
+        }
+
+        is(LessThanUnsigned) {
+            io.out := io.a < io.b
+        }
+
+        is(LessThanSigned) {
+            io.out := io.a.asSInt < io.b.asSInt
+        }
     }
-  }
 
 }