Stage 6: implementation, untested

bench/op/addi.s

@@ -0,0 +1,18 @@
+# expected: dead0000, dead0001, fffff800, ffffffff, 00000000
+    .text
+_start:
+    lui x2, 0xdead0
+    lui x3, 0x0
+
+    # Add 0
+    addi x31, x2, 0x0
+
+    # Basic addition
+    addi x31, x2, 0x1
+
+    # Sign extension
+    addi x31, x3, -2048
+    addi x31, x3, -1
+
+    # Overflow
+    addi x31, x31, 0x1

bench/op/andi.s

@@ -0,0 +1,9 @@
+# expected: 00000000, 00000010
+    .text
+_start:
+    addi x1, x0, 0x100
+    andi x31, x1, 0x0FF
+
+    addi x1, x0, -1
+    andi x31, x1, 0x010
+

bench/op/auipc.s

@@ -0,0 +1,6 @@
+# expected: 0000a000,0000b004,0000c008
+    .text
+_start:
+    auipc x31, 0xa
+    auipc x31, 0xb
+    auipc x31, 0xc

bench/op/lui.s

@@ -0,0 +1,7 @@
+# expected: 00000000,FFFFF000,12345000
+	.text
+
+	lui x31, 0       #Test chargement d'une valeur nulle
+	lui x31, 0xfffff #Test chargement d'une valeur maximal sur 20 bits
+	lui x31, 0x12345 #Test chargement d'une valeur quelconque
+

bench/op/ori.s

@@ -0,0 +1,4 @@
+# expected: 00000000, 00000010
+    .text
+_start:
+