Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa

src/test/scala/projet/ZzTopAllSpec.scala

@@ -5,11 +5,12 @@ import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.must.Matchers
 import java.nio.file.{Files, Paths}
 import scala.jdk.CollectionConverters._
-import scala.io.Source
 import scala.collection.mutable.ListBuffer
 import java.nio.file.FileSystems
 import java.nio.file.Path
 import org.scalatest.ParallelTestExecution
+import projet.ZzTopCommon.expectedValuesFromAsm
+import projet.ZzTopCommon.expectNextValue
 
 class ZzTopAllSpec
     extends AnyFreeSpec
@@ -17,60 +18,6 @@ class ZzTopAllSpec
     with ParallelTestExecution
     with ChiselSim {
 
-    def expectedValuesFromAsm(path: String): Seq[BigInt] = {
-        val line =
-            Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
-        line match {
-            case Some(l) =>
-                l.stripPrefix("# expected:")
-                    .split(",")
-                    .map(_.trim)
-                    .filter(_.nonEmpty)
-                    .map(str => BigInt(str, 16))
-                    .toSeq
-            case None =>
-                Seq.empty
-        }
-    }
-
-    def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
-        val prefix = s"🛑 $msg\n"
-        val traceStr =
-            if (trace.nonEmpty)
-                "Trace:\n" + trace.map("  - " + _).mkString("\n") + "\n"
-            else ""
-        fail(prefix + traceStr)
-    }
-
-    def expectNextValue(
-        dut: ZzTop,
-        expected: BigInt,
-        timeout: Int,
-        trace: ListBuffer[String]
-    ): Unit = {
-        var cycles = 0
-        val clock_per_cpucycle = 2;
-        dut.clock.step(
-            clock_per_cpucycle
-        ) // Attente d'un cycle proc (clock_per_cpu cycles systeme)
-        // Attendre une écriture dans x31
-        while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
-            dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
-            cycles += 1
-            trace += f"Attente $cycles cycles"
-        }
-
-        if (cycles < timeout) {
-            // Vérifier la nouvelle valeur
-            val got = dut.io.x31.get.peek().litValue
-            trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
-            if (got != expected) failTrace("Mauvaise sortie", trace)
-        } else {
-            trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
-            failTrace("Simulation bloquée", trace)
-        }
-    }
-
     // Fonction de test commune
     def testWith(file: String): Unit = {
         val path = file.replace("/mem/", "/").replace(".mem", ".s")
@@ -92,10 +39,6 @@ class ZzTopAllSpec
 
     val dir =
         FileSystems.getDefault().getPath(sys.env("PROOT") + "/bench/mem/tests")
-    // val suffix = ".mem"
-
-    // val path = dir + name + suffix
-    // print(path)
 
     var tests = Files
         .walk(dir)

src/test/scala/projet/ZzTopCommon.scala

@@ -0,0 +1,62 @@
+package projet
+
+import scala.io.Source
+import scala.collection.mutable.ListBuffer
+import org.scalatest.freespec.AnyFreeSpec
+import chisel3.simulator.scalatest.ChiselSim
+
+object ZzTopCommon extends AnyFreeSpec with ChiselSim {
+    def expectedValuesFromAsm(path: String): Seq[BigInt] = {
+        val line =
+            Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
+        line match {
+            case Some(l) =>
+                l.stripPrefix("# expected:")
+                    .split(",")
+                    .map(_.trim)
+                    .filter(_.nonEmpty)
+                    .map(str => BigInt(str, 16))
+                    .toSeq
+            case None =>
+                Seq.empty
+        }
+    }
+
+    def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
+        val prefix = s"🛑 $msg\n"
+        val traceStr =
+            if (trace.nonEmpty)
+                "Trace:\n" + trace.map("  - " + _).mkString("\n") + "\n"
+            else ""
+        fail(prefix + traceStr)
+    }
+
+    def expectNextValue(
+        dut: ZzTop,
+        expected: BigInt,
+        timeout: Int,
+        trace: ListBuffer[String]
+    ): Unit = {
+        var cycles = 0
+        val clock_per_cpucycle = 2;
+        dut.clock.step(
+            clock_per_cpucycle
+        ) // Attente d'un cycle proc (clock_per_cpucycle cycles systeme)
+        // Attendre une écriture dans x31
+        while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
+            dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
+            cycles += 1
+            trace += f"Attente $cycles cycles"
+        }
+
+        if (cycles < timeout) {
+            // Vérifier la nouvelle valeur
+            val got = dut.io.x31.get.peek().litValue
+            trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
+            if (got != expected) failTrace("Mauvaise sortie", trace)
+        } else {
+            trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
+            failTrace("Simulation bloquée", trace)
+        }
+    }
+}

src/test/scala/projet/ZzTopSpec.scala

@@ -6,65 +6,11 @@ import org.scalatest.matchers.must.Matchers
 import org.scalatest.prop.TableDrivenPropertyChecks._
 import java.nio.file.{Files, Paths}
 import scala.jdk.CollectionConverters._
-import scala.io.Source
 import scala.collection.mutable.ListBuffer
+import projet.ZzTopCommon.expectedValuesFromAsm
+import projet.ZzTopCommon.expectNextValue
 
 class ZzTopSpec extends AnyFreeSpec with Matchers with ChiselSim {
-
-    def expectedValuesFromAsm(path: String): Seq[BigInt] = {
-        val line =
-            Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
-        line match {
-            case Some(l) =>
-                l.stripPrefix("# expected:")
-                    .split(",")
-                    .map(_.trim)
-                    .filter(_.nonEmpty)
-                    .map(str => BigInt(str, 16))
-                    .toSeq
-            case None =>
-                Seq.empty
-        }
-    }
-
-    def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
-        val prefix = s"🛑 $msg\n"
-        val traceStr =
-            if (trace.nonEmpty)
-                "Trace:\n" + trace.map("  - " + _).mkString("\n") + "\n"
-            else ""
-        fail(prefix + traceStr)
-    }
-
-    def expectNextValue(
-        dut: ZzTop,
-        expected: BigInt,
-        timeout: Int,
-        trace: ListBuffer[String]
-    ): Unit = {
-        var cycles = 0
-        val clock_per_cpucycle = 2;
-        dut.clock.step(
-            clock_per_cpucycle
-        ) // Attente d'un cycle proc (clock_per_cpucycle cycles systeme)
-        // Attendre une écriture dans x31
-        while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
-            dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
-            cycles += 1
-            trace += f"Attente $cycles cycles"
-        }
-
-        if (cycles < timeout) {
-            // Vérifier la nouvelle valeur
-            val got = dut.io.x31.get.peek().litValue
-            trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
-            if (got != expected) failTrace("Mauvaise sortie", trace)
-        } else {
-            trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
-            failTrace("Simulation bloquée", trace)
-        }
-    }
-
     // Fonction de test commune
     def testWith(file: String): Unit = {
         val path = file.replace("/mem/", "/").replace(".mem", ".s")