Fixs merge conflict with word mode

src/main/scala/projet/ControlUnit.scala

@@ -9,8 +9,6 @@ import projet.op.OpBranch
 import projet.op.OpStore
 import projet.op.OpLoad
 import projet.op.OpImmW
-import projet.op.OpM
-import projet.op.OpRW
 
 class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
@@ -98,9 +96,6 @@ object OpCode extends ChiselEnum {
     // add, and, or, xor, sll, srl, sra, slt, stlu, mul, mulh, mulhsu, mulhu, div, divu, rem, remu
     val OpR = "b0110011".U;
 
-    // mulw, divw, remw
-    val OpMw = "b0111011".U;
-
     // Type J
     val JAL = "b1101111".U
 
@@ -206,11 +201,6 @@ class ControlUnit() extends Module {
             OpR.opR(io);
         }
 
-        is(OpCode.OpMw) {
-            io.alu_word_mode := true.B
-            OpM.opM(io);
-        }
-
         is(OpCode.OpBranch) {
             OpBranch.opBranch(io);
         }
@@ -228,7 +218,8 @@ class ControlUnit() extends Module {
         }
 
         is(OpCode.OpRW) {
-            OpRW.opRW(io);
+            io.alu_word_mode := true.B
+            OpR.opR(io);
         }
     }
 }

src/main/scala/projet/op/OpRW.scala

@@ -1,70 +0,0 @@
-package projet.op
-
-import chisel3._
-import chisel3.util.switch
-import projet.CUInterface
-import projet.AluOpCode
-import chisel3.util.is
-
-object OpRW {
-    // Implements functions for all instruction of the opImm, w  kind
-    def opRW(io: CUInterface) = {
-        val funct3 = io.instruction(14, 12);
-        val funct7 = io.instruction(31, 25);
-
-        // Meaning of Funct3 in the context of an OpImm instruction
-        object Funct3 extends ChiselEnum {
-            // Type I
-            val AdditionSubstraction = "b000".U
-            val SLLW = "b001".U
-            val ShiftRight = "b101".U
-
-            // Unimplemented
-            val ShiftWordRight = "b101".U // Right shifts
-        }
-
-        object AdditionSubstractionFunct7 extends ChiselEnum {
-            val ADDW = "b0000000".U
-            val SUBW = "b0100000".U
-        }
-
-        object ShiftWordRightFunct7 extends ChiselEnum {
-            val SRLW = "b0000000".U
-            val SRAW = "b0100000".U
-        }
-
-        io.reg_file_we := true.B // Write to regfile
-        io.alu_word_mode := true.B
-        io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
-        io.mux_rega_pc := true.B;
-        io.mux_alu_imm := true.B;
-        switch(funct3) {
-            // Type I
-            is(Funct3.AdditionSubstraction) {
-                switch(funct7) {
-                    is(AdditionSubstractionFunct7.ADDW) {
-                        io.alu_opcode := AluOpCode.Add
-                    }
-                    is(AdditionSubstractionFunct7.SUBW) {
-                        io.alu_opcode := AluOpCode.Sub
-                    }
-                }
-            }
-
-            is(Funct3.SLLW) {
-                io.alu_opcode := AluOpCode.ShiftLeft
-            }
-
-            is(Funct3.ShiftWordRight) {
-                switch(funct7) {
-                    is(ShiftWordRightFunct7.SRAW) {
-                        io.alu_opcode := AluOpCode.ShiftArithmeticRight
-                    }
-                    is(ShiftWordRightFunct7.SRLW) {
-                        io.alu_opcode := AluOpCode.ShiftRight
-                    }
-                }
-            }
-        }
-    }
-}