Implements stage 6: tests passing

bench/tests/op/ori.s

@@ -1,4 +1,9 @@
-# expected: 00000000, 00000010
+# expected: 000001FF, FFFFFFFF
     .text
 _start:
+    addi x1, x0, 0x100
+    ori x31, x1, 0x0FF
+
+    addi x1, x0, -1
+    ori x31, x1, 0x010
 

bench/tests/op/slli.s

@@ -0,0 +1,11 @@
+# expected: 000003FC, 80000000, 00000000
+    .text
+_start:
+    addi x1, x0, 0x0FF
+    slli x31, x1, 2
+
+    addi x1, x0, 0x001
+    slli x31, x1, 31
+
+    addi x1, x0, 0x0F0
+    slli x31, x1, 31

bench/tests/op/slti.s

@@ -0,0 +1,15 @@
+# expected: 00000000, 00000001, 00000001, 00000000
+    .text
+_start:
+    addi x1, x0, (-1)
+    slti x31, x1, (-37)
+
+    addi x1, x0, (-37)
+    slti x31, x1, (-1)
+
+    addi x1, x0, (-38)
+    slti x31, x1, 29
+
+    addi x1, x0, 129
+    slti x31, x1, (-7)
+

bench/tests/op/sltiu.s

@@ -0,0 +1,11 @@
+# expected: 00000001, 00000001, 00000000
+    .text
+_start:
+    addi x1, x0, 0
+    sltiu x31, x1, (-1)
+
+    addi x1, x0, 98
+    sltiu x31, x1, 99
+
+    addi x1, x0, 99
+    sltiu x31, x1, 98

bench/tests/op/srai.s

@@ -0,0 +1,11 @@
+# expected: 000000FF, FFFFFFFF, 00000000
+    .text
+_start:
+    addi x1, x0, 0x3FC
+    srai x31, x1, 2
+
+    lui x1, 0xA0000
+    srai x31, x1, 31
+
+    lui x1, 0x0A000
+    srai x31, x1, 31

bench/tests/op/srli.s

@@ -0,0 +1,11 @@
+# expected: 000000FF, 00000001, 00000000
+    .text
+_start:
+    addi x1, x0, 0x3FC
+    srli x31, x1, 2
+
+    lui x1, 0xA0000
+    srli x31, x1, 31
+
+    lui x1, 0x0A000
+    srli x31, x1, 31

bench/tests/op/xori.s

@@ -0,0 +1,12 @@
+# expected: 00000000, 000001EF
+    .text
+_start:
+    # 1 XOR 1 should equal 0000000
+    addi x1, x0, -1
+    xori x31, x1, -1
+
+    addi x1, x0, 0x1BC
+
+    # Xor is involutive and commutative, applying it twice should give us the original operand
+    xori x1, x1, 0x1EF
+    xori x31, x1, 0x1BC

src/main/scala/projet/ControlUnit.scala

@@ -80,23 +80,23 @@ class ControlUnit() extends Module {
       object Funct3 extends ChiselEnum
       {
         // Type I
-        val ADDI = 000.U
+        val ADDI = 0b000.U
-        val SLTI = 010.U
+        val SLTI = 0b010.U
-        val SLTIU = 011.U
+        val SLTIU = 0b011.U
-        val XORI = 100.U
+        val XORI = 0b100.U
-        val ORI = 110.U
+        val ORI = 0b110.U
-        val ANDI = 111.U
+        val ANDI = 0b111.U
 
         // Type IR
-        val SLLI = 001.U
+        val SLLI = 0b001.U
-        val SRLI_SRAI = 101.U // Right shifts
+        val SRLI_SRAI = 0b101.U // Right shifts
       }
 
       // Meaning of Funct7 in the context of SHIFTR IR instructions 
       object IRFunct7 extends ChiselEnum
       {
-        val SRLI = 0000000.U 
+        val SRLI = 0b0000000.U 
-        val SRAI = 0100000.U 
+        val SRAI = 0b0100000.U 
       }
        switch(funct3)
        {
@@ -131,6 +131,18 @@ class ControlUnit() extends Module {
             io.optype := OpType.I
           }
 
+          is(Funct3.SLTI)
+          {
+            io.alu_opcode := AluOpCode.LessThanSigned
+            io.optype := OpType.I
+          }
+
+          is(Funct3.SLTIU)
+          {
+            io.alu_opcode := AluOpCode.LessThanUnsigned
+            io.optype := OpType.I
+          }
+
           // Type IR
           is(Funct3.SRLI_SRAI)
           {