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Implements stage 6: tests passing

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This commit is contained in:
Albin Chaboissier
2025-11-06 18:38:32 +01:00
parent 2ee9cc66b9
commit 1c829366de
10 changed files with 99 additions and 11 deletions
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32
src/main/scala/projet/ControlUnit.scala
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@@ -80,23 +80,23 @@ class ControlUnit() extends Module {
object Funct3 extends ChiselEnum
{
// Type I
val ADDI = 000.U
val SLTI = 010.U
val SLTIU = 011.U
val XORI = 100.U
val ORI = 110.U
val ANDI = 111.U
val ADDI = 0b000.U
val SLTI = 0b010.U
val SLTIU = 0b011.U
val XORI = 0b100.U
val ORI = 0b110.U
val ANDI = 0b111.U
// Type IR
val SLLI = 001.U
val SRLI_SRAI = 101.U // Right shifts
val SLLI = 0b001.U
val SRLI_SRAI = 0b101.U // Right shifts
}
// Meaning of Funct7 in the context of SHIFTR IR instructions
object IRFunct7 extends ChiselEnum
{
val SRLI = 0000000.U
val SRAI = 0100000.U
val SRLI = 0b0000000.U
val SRAI = 0b0100000.U
}
switch(funct3)
{
@@ -131,6 +131,18 @@ class ControlUnit() extends Module {
io.optype := OpType.I
}
is(Funct3.SLTI)
{
io.alu_opcode := AluOpCode.LessThanSigned
io.optype := OpType.I
}
is(Funct3.SLTIU)
{
io.alu_opcode := AluOpCode.LessThanUnsigned
io.optype := OpType.I
}
// Type IR
is(Funct3.SRLI_SRAI)
{