Implements stage 5

src/main/scala/projet/Rv32i.scala

@@ -1,7 +1,6 @@
 package projet
 
 import chisel3._
-import chisel3.util.Cat
 
 class Rv32i(sim: Boolean = true) extends Module {
     val io = IO(new Bundle {
@@ -18,12 +17,15 @@ class Rv32i(sim: Boolean = true) extends Module {
     reg_file.io.rd_data := 0.U;
     io.x31 := reg_file.io.x31
     if (sim) {
-        io.valid_x31.get := reg_file.io.valid_x31.get
+        io.valid_x31.get := reg_file.io.valid_x31.get && Delay.Delay(!reset.asBool, 1, false.B)
     }
 
     val alu = Module(new Alu());
+    val immediate_decoder = Module(new ImmediateDecoder());
     val control_unit = Module(new ControlUnit());
 
+    immediate_decoder.io.instruction := instruction
+    immediate_decoder.io.op_type := control_unit.io.optype
     alu.io.opcode := control_unit.io.alu_opcode;
     reg_file.io.we := control_unit.io.reg_file_we
 
@@ -49,16 +51,19 @@ class Rv32i(sim: Boolean = true) extends Module {
     val rd = instruction(11, 7)
     reg_file.io.rd_addr := rd
 
-    // Decode imm-u
-    val imm_u = Cat(instruction(31, 12), 0.U(12.W));
-
     // EXECUTE
-    
-    alu.io.a := execute_pc;
-    alu.io.b := imm_u;
 
-    reg_file.io.rd_data := Mux(control_unit.io.mux_imm_alu, alu.io.out, imm_u);
-  
+    val imm = immediate_decoder.io.immediate
+
+    alu.io.a := Mux(
+        control_unit.io.mux_rega_pc,
+        reg_file.io.rs1_data,
+        execute_pc
+    );
+    alu.io.b := imm;
+
+    reg_file.io.rd_data := Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);
+
     io.dbus.addr := 0.U;
     io.dbus.wdata := 0.U;
     io.dbus.be := VecInit(false.B, false.B, false.B, false.B)