Implements stage 5

src/main/scala/projet/RegFile.scala

@@ -25,25 +25,21 @@ class RegFile(sim: Boolean = false) extends Module {
     }
 
     when(io.we && io.rd_addr =/= 0.U) {
-      regs(io.rd_addr) := io.rd_data
+        regs(io.rd_addr) := io.rd_data
     }
 
     io.rs1_data := regs(io.rs1_addr)
     io.rs2_data := regs(io.rs2_addr)
 
     // Simulation stuff
-    val valid = WireInit(false.B);
-    when(io.we && io.rd_addr === 31.U)
-    {
-      io.x31 := io.rd_data  
-      if (sim) {
-          valid := true.B
-      }
-    }.otherwise
-    {
-      io.x31 := regs(31)
-    }
     if (sim) {
-      io.valid_x31.get := Delay.Delay(valid, 1, false.B)
+        io.valid_x31.get := false.B
+    }
+    io.x31 := "hDEADC0DE".U
+    when(io.we && io.rd_addr === 31.U) {
+        io.x31 := io.rd_data
+        if (sim) {
+            io.valid_x31.get := true.B
+        }
     }
 }