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Changes binary notation in ControlUnit to make formatter happy

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This commit is contained in:
Albin Chaboissier
2025-11-07 10:41:09 +01:00
parent 1adf33810f
commit 0e991583b9
1 changed files with 163 additions and 177 deletions
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78
src/main/scala/projet/ControlUnit.scala
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@@ -24,8 +24,8 @@ object OpType extends ChiselEnum {
object OpCode extends ChiselEnum {
// Type U
val LUI = 0b0110111.U
val AUIPC = 0b0010111.U
val LUI = "b0110111".U
val AUIPC = "b0010111".U
// Type I + Type IR
@@ -36,7 +36,7 @@ object OpCode extends ChiselEnum {
// addi, andi, ori, xori, slli, srli, srai,
// slti, sltiu
val OpImm = 0b0010011.U
val OpImm = "b0010011".U
// Instruction format
// xxx rd, rs1, rs2
@@ -44,11 +44,10 @@ object OpCode extends ChiselEnum {
// and writes back to a register
// add, and, or, xor, sll, srl, sra, slt, stlu
val OpR = 0b0110011.U;
val OpR = "b0110011".U;
}
class ControlUnit() extends Module {
val io = IO(new CUInterface())
@@ -93,39 +92,33 @@ class ControlUnit() extends Module {
}
}
// Implements functions for all instruction of the opImm kind
def opImm(funct3: UInt, funct7: UInt, io: CUInterface) =
{
def opImm(funct3: UInt, funct7: UInt, io: CUInterface) = {
// Meaning of Funct3 in the context of an OpImm instruction
object Funct3 extends ChiselEnum
{
object Funct3 extends ChiselEnum {
// Type I
val ADDI = 0b000.U
val SLTI = 0b010.U
val SLTIU = 0b011.U
val XORI = 0b100.U
val ORI = 0b110.U
val ANDI = 0b111.U
val ADDI = "b000".U
val SLTI = "b010".U
val SLTIU = "b011".U
val XORI = "b100".U
val ORI = "b110".U
val ANDI = "b111".U
// Type IR
val SLLI = 0b001.U
val SRLI_SRAI = 0b101.U // Right shifts
val SLLI = "b001".U
val SRLI_SRAI = "b101".U // Right shifts
}
// Meaning of Funct7 in the context of SHIFTR IR instructions
object IRFunct7 extends ChiselEnum
{
val SRLI = 0b0000000.U
val SRAI = 0b0100000.U
object IRFunct7 extends ChiselEnum {
val SRLI = "b0000000".U
val SRAI = "b0100000".U
}
io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
io.mux_alu_imm := true.B;
io.mux_rega_pc := true.B;
switch(funct3)
{
switch(funct3) {
// Type I
is(Funct3.ADDI)
{
@@ -189,38 +182,33 @@ class ControlUnit() extends Module {
}
}
// Implements functions for all instruction of the opR kind
def opR(funct3: UInt, funct7: UInt, io: CUInterface) =
{
def opR(funct3: UInt, funct7: UInt, io: CUInterface) = {
// Meaning of Funct3 in the context of an OpR instruction
object Funct3 extends ChiselEnum
{
object Funct3 extends ChiselEnum {
// Type I
val ADD = 0b000.U
val AND = 0b111.U
val OR = 0b110.U
val XOR = 0b100.U
val SLL = 0b001.U
val SLT = 0b010.U
val SLTU = 0b011.U
val ADD = "b000".U
val AND = "b111".U
val OR = "b110".U
val XOR = "b100".U
val SLL = "b001".U
val SLT = "b010".U
val SLTU = "b011".U
// Arithmetic op (discriminate by Funct7)
val SRL_SRA = 0b101.U
val SRL_SRA = "b101".U
}
// Meaning of Funct7 in the context of SHIFTR IR instructions
object IRFunct7 extends ChiselEnum
{
val SRL = 0b0000000.U
val SRA = 0b0100000.U
object IRFunct7 extends ChiselEnum {
val SRL = "b0000000".U
val SRA = "b0100000".U
}
io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
io.mux_rega_pc := true.B;
io.mux_alu_imm := true.B;
switch(funct3)
{
switch(funct3) {
// Type I
is(Funct3.ADD)
{
@@ -276,5 +264,3 @@ class ControlUnit() extends Module {
}
}
}