Adds a way to simulate the programs with spike, to compare PCs and debug

src/main/scala/projet/Rv64i.scala

@@ -10,7 +10,7 @@ class Rv64i(sim: Boolean = true) extends Module {
         val valid_x31 = if (sim) Some(Output(Bool())) else None
     })
 
-    val reg_pc = RegInit(0.U(64.W));
+    val reg_pc = RegInit("x10000".U(64.W));
     val reg_file = Module(new RegFile(sim));
 
     reg_file.io.rd_data := 0.U;
@@ -33,10 +33,17 @@ class Rv64i(sim: Boolean = true) extends Module {
     alu.io.word_mode := control_unit.io.alu_word_mode
 
     // PC delayed to execute stage for auipc op
-    val execute_pc = Delay.Delay(reg_pc, 1, 0.U);
+    val execute_pc = Delay.Delay(reg_pc, 1, "x10000".U(64.W));
     // True if the instruction in the execute stage is a jump
     val is_jump = Delay.Delay(control_unit.io.is_jump, 1, false.B);
 
+    if (sim) {
+        val log = SimLog.file("core_pc.log");
+        when(!is_jump) {
+            log.printf(cf"0x${execute_pc}%x\n")
+        }
+    }
+
     // Pipelining registers for mem stage
     val reg_rd_index = RegInit(0.U);
     val reg_execute_out = RegInit(0.U);