Stage 9: Full implemntation + passing tests

src/main/scala/projet/ControlUnit.scala

@@ -8,6 +8,9 @@ class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
     val reg_file_we = Output(Bool())
     val alu_opcode = Output(AluOpCode())
+    // Alu comparison result
+    val alu_comp_result = Input(Bool())
+
     val optype = Output(OpType())
 
     // True if the decoded instruction is a jump
@@ -40,7 +43,7 @@ class CUInterface extends Bundle {
 }
 
 object OpType extends ChiselEnum {
-    val U, I, IR, J = Value
+    val U, I, IR, J, B = Value
 }
 
 object OpCode extends ChiselEnum {
@@ -72,6 +75,9 @@ object OpCode extends ChiselEnum {
 
     // Type I
     val JALR = "b1100111".U
+
+    // Type B
+    val OpBranch = "b1100011".U
 }
 
 class ControlUnit() extends Module {
@@ -153,6 +159,11 @@ class ControlUnit() extends Module {
             io.mux_pcadder_writeback := false.B; // Set pc to writeback dest
             io.optype := OpType.I
         }
+
+        is(OpCode.OpBranch) {
+            io.optype := OpType.B;
+            opBranch(funct3, io);
+        }
     }
 
     // Implements functions for all instruction of the opImm kind
@@ -304,4 +315,78 @@ class ControlUnit() extends Module {
             }
         }
     }
+
+    // Implements functions for all instruction of the branch kind
+    def opBranch(funct3: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpBranch instruction
+        object Funct3 extends ChiselEnum {
+            val BEQ = "b000".U
+            val BNE = "b001".U
+            val BLT = "b100".U
+            val BGE = "b101".U
+            val BLTU = "b110".U
+            val BGEU = "b111".U
+        }
+
+        val branch = WireInit(false.B);
+        switch(funct3) {
+            is(Funct3.BEQ) {
+                // Send operands from registers to alu
+                io.alu_opcode := AluOpCode.Equal
+                io.mux_rega_pc := true.B;
+                io.mux_regb_imm := true.B;
+                branch := io.alu_comp_result
+            }
+
+            is(Funct3.BNE) {
+                // Send operands from registers to alu
+                io.alu_opcode := AluOpCode.Equal
+                io.mux_rega_pc := true.B;
+                io.mux_regb_imm := true.B;
+                branch := ~io.alu_comp_result
+            }
+
+            // Signed comparison
+            is(Funct3.BLT) {
+                // Send operands from registers to alu
+                io.alu_opcode := AluOpCode.LessThanSigned
+                io.mux_rega_pc := true.B;
+                io.mux_regb_imm := true.B;
+                branch := io.alu_comp_result
+            }
+
+            is(Funct3.BGE) {
+                // Send operands from registers to alu
+                io.alu_opcode := AluOpCode.LessThanSigned
+                io.mux_rega_pc := true.B;
+                io.mux_regb_imm := true.B;
+                branch := ~io.alu_comp_result
+            }
+
+            // Signed comparison
+            is(Funct3.BLTU) {
+                // Send operands from registers to alu
+                io.alu_opcode := AluOpCode.LessThanUnsigned
+                io.mux_rega_pc := true.B;
+                io.mux_regb_imm := true.B;
+                branch := io.alu_comp_result
+            }
+
+            is(Funct3.BGEU) {
+                // Send operands from registers to alu
+                io.alu_opcode := AluOpCode.LessThanUnsigned
+                io.mux_rega_pc := true.B;
+                io.mux_regb_imm := true.B;
+                branch := ~io.alu_comp_result
+            }
+        }
+
+        // Branch if comparison is successful
+        when(branch) {
+            io.mux_pcadder_writeback := true.B;
+            io.mux_incrpc4_imm := false.B;
+            io.mux_regpc_executepc := false.B;
+            io.is_jump := true.B;
+        }
+    }
 }