Stage 9: Full implemntation + passing tests

src/main/scala/projet/Alu.scala

@@ -6,8 +6,8 @@ import chisel3.util.is
 
 object AluOpCode extends ChiselEnum {
     val Add, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
-        LessThanSigned, LessThanUnsigned, GreaterEqualSigned, GreaterEqualUnsigned,
-        Equal = Value
+        LessThanSigned, LessThanUnsigned, GreaterEqualSigned,
+        GreaterEqualUnsigned, Equal = Value
 }
 
 class Alu extends Module {
@@ -22,7 +22,7 @@ class Alu extends Module {
     })
 
     io.out := 0.U;
-    io.flags := false.B;
+    io.comp_result := false.B;
     switch(io.opcode) {
         is(Add) {
             io.out := io.a + io.b;
@@ -60,25 +60,25 @@ class Alu extends Module {
         }
 
         is(LessThanSigned) {
-            val less_than := io.a.asSInt < io.b.asSInt
+            val less_than = io.a.asSInt < io.b.asSInt
             io.out := less_than
             io.comp_result := less_than;
         }
-        
+
         is(GreaterEqualUnsigned) {
-            val geq_than = io.a >== io.b;
+            val geq_than = io.a >= io.b;
             io.out := geq_than
             io.comp_result := geq_than;
         }
 
         is(GreaterEqualSigned) {
-          val geq_than := io.a.asSInt >== io.b.asSInt
+            val geq_than = io.a.asSInt >= io.b.asSInt
             io.out := geq_than
             io.comp_result := geq_than;
         }
 
         is(Equal) {
-            io.comp_result := io.& === io.b;
+            io.comp_result := io.a === io.b;
         }
     }