Rv64i : passing test

src/main/scala/projet/ControlUnit.scala

@@ -9,6 +9,7 @@ import projet.op.OpBranch
 import projet.op.OpStore
 import projet.op.OpLoad
 import projet.op.OpImmW
+import projet.op.OpRW
 
 class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
@@ -113,6 +114,9 @@ object OpCode extends ChiselEnum {
 
     // ~~ Rv64i ~~
     val OpImmW = "b0011011".U
+
+    // TypeR
+    val OpRW = "b0111011".U
 }
 
 class ControlUnit() extends Module {
@@ -213,5 +217,9 @@ class ControlUnit() extends Module {
         is(OpCode.OpImmW) {
             OpImmW.opImmW(io);
         }
+
+        is(OpCode.OpRW) {
+            OpRW.opRW(io);
+        }
     }
 }

src/main/scala/projet/DMem.scala

@@ -80,7 +80,7 @@ class DMem extends Module {
     }
 
     // Data out is available one cycle after the read request
-    val read_addr = Delay.Delay(io.addr, 2, 0.U);
+    val read_addr = Delay.Delay(io.addr, 1, 0.U);
     val read_sign_extend = Delay.Delay(io.sign_extend, 1, false.B);
     when(Delay.Delay(io.en && !io.we, 1, false.B)) {
         switch(Delay.Delay(io.size, 1, DMemSize.Byte)) {

src/main/scala/projet/op/OpLoad.scala

@@ -39,6 +39,7 @@ object OpLoad {
         io.reg_file_we := true.B
         io.memory_en := true.B
         io.memory_we := false.B
+        io.memory_sign_extend := false.B;
         switch(funct3) {
             // Byte load
             is(Funct3.LB) {
@@ -61,16 +62,15 @@ object OpLoad {
             // Word load
             is(Funct3.LW) {
                 io.memory_size := DMemSize.Word
+                io.memory_sign_extend := true.B;
             }
             is(Funct3.LWU) {
                 io.memory_size := DMemSize.Word
-                io.memory_sign_extend := true.B;
             }
 
             // Long load
             is(Funct3.LD) {
                 io.memory_size := DMemSize.Long
-                io.memory_sign_extend := true.B;
             }
         }
     }

src/main/scala/projet/op/OpRW.scala

@@ -5,7 +5,6 @@ import chisel3.util.switch
 import projet.CUInterface
 import projet.AluOpCode
 import chisel3.util.is
-import projet.OpType
 
 object OpRW {
     // Implements functions for all instruction of the opImm, w  kind