Rv64i : passing test

2025-11-13 09:49:18 +01:00
parent 7bb8b993ae
commit 030149cbea
16 changed files with 166 additions and 6 deletions
--- a/bench/tests/op/srlw.s
+++ b/bench/tests/op/srlw.s
@@ -0,0 +1,22 @@
+# expected: 0000000000000000, 000000003fffffff, 0000000040000000, 0000000000000000
+    .text
+_start:
+    # Test 1:  1 >> 1  => 0
+    li    x1, 1
+    li    x2, 1
+    srlw x31, x1, x2   # x31 = 0
+
+    # Test 2:  0x7fffffff >> 1  => 0x3fffffff
+    li    x1, 0x7fffffff
+    li x2, 1
+    srlw x31, x1, x2   # x31 = 0x000000003fffffff
+
+    # Test 3:  0x80000000 >> 1  => 0x40000000 (not sign-extended)
+    li    x1, 0x80000000
+    li x2, 1
+    srlw x31, x1, x2   # x31 = 0xffffffffc0000000
+
+    li x1, 0x40000000
+    li x2, 33
+    srlw x31, x1, x2
+