package projet

import chisel3.Data
import chisel3.RegInit

object Delay {
    def Delay[T <: Data](x: T, n: Int, init: T): T = {
        require(n >= 0)
        if (n == 0) x
        else {
            val reg = RegInit(init);
            reg := Delay(x, n - 1, init)
            reg
        }
    }
}
