1.8 KiB
1.8 KiB
Example
This directory shows how to flash a SystemVerilog program (a full-adder) on a Zybo xc7z010clg400-1 board.
Build
Firstly, the SystemVerilog file needs to be converted to verilog to use it with Yosys :
podman run --mount=type=bind,source=.,target=/root/code fmn_alpine sv2v adder.sv -w adder.v
The mount parameter is used to provide the current directory to podman.
Then, Yosys can perform the RTL synthesis of the program :
podman run --mount=type=bind,source=.,target=/root/code fmn_alpine yosys adder.v -p "synth_xilinx; write_json synthesis.json"
Nextpnr can now place and route each component using the XDC constraints file :
podman run --mount=type=bind,source=.,target=/root/code fmn_alpine nextpnr-himbaechel --json synthesis.json -o xdc=adder.xdc -o fasm=out.fasm --device xc7z010clg400-1
Now the FASM file can be converted to a frames file and then to a bitstream :
podman run --mount=type=bind,source=.,target=/root/code fmn_alpine fasm2frames --part xc7z010clg400-1 --db-root /usr/share/xray/database/zynq7 out.fasm out.frames
podman run --mount=type=bind,source=.,target=/root/code fmn_alpine xc7frames2bit -frm_file out.frames -part_file /usr/share/xray/database/zynq7/xc7z010clg400-1/part.yaml --output_file out.bin
Flashing the FPGA
Finally, we can flash the bitstream on the board with openFPGALoader.
Podman requires a device argument to allow openFPGALoader to access the USB interface. You can find this path with lsusb :
Bus 003 Device 005: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
Here the usb device path is /dev/bus/usb/003/005
podman run --device=/dev/bus/usb/003/005 --mount=type=bind,source=.,target=/root/code fmn_alpine openFPGALoader -b zybo_z7_10 out.bin