diff --git a/README.md b/README.md
index 5e9a85a..7487a8b 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
-This repository contains a podman image whichs contains all necessary tools to generate and flash bitstream file from a SystemVerilog program.
-It is build for the xilinx zybo zynq7 `xc7z010` card, but it can probably be easily edited to support another card.
+This repository contains a podman image whichs includes all the necessary tools to generate and flash a bitstream file from a SystemVerilog program.
+It is built for the Xilinx Zybo Zynq7 `xc7z010` card, but it can probably be easily adapted to support another board.
 
 # Installation
 
@@ -7,7 +7,7 @@ You will need [podman](https://podman.io/) to run the image.
 
 ## Use the pre-built image
 
-You can directly use the pre-build image present in the repo
+You can directly use the pre-built image available in the repository :
 
 ```bash
 zstd -d fmn.tar.zst
@@ -16,27 +16,27 @@ podman load --input fmn.tar
 
 ## Build the image from source
 
-You can build the image yourself by using this command:
+You can build the image yourself by using this command :
 
 ```bash
 podman build -t fmn_alpine .
 ```
 
-It will first create an image which will build every tools, and then create the final image containing only needed binaries and libraries.
+It will first create an image that builds all the tools, and then generate the final image containing only the necessary binaries and libraries.
 
-For information, it takes around 5.63GB space and 10 minutes to build on my device.
+For reference, it takes about 5.63GB of space and 10 minutes to build on my machine.
 
 # Tools
 
-- [sv2v](https://github.com/zachjs/sv2v) : Convert SystemVerilog to Verilog.
-- [yosys](https://github.com/YosysHQ/yosys) : Do RTL synthesis from verilog files.
+- [sv2v](https://github.com/zachjs/sv2v) : Converts SystemVerilog to Verilog.
+- [yosys](https://github.com/YosysHQ/yosys) : Performs RTL synthesis from verilog files.
 - [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) : placing and routing tool.
-- [fasm2frames](https://github.com/f4pga/prjxray) : Convert fasm files to frames files.
-- [xc7frames2bit](https://github.com/f4pga/prjxray) : Convert frames files to bitstream.
-- [openFPGALoader](https://github.com/trabucayre/openFPGALoader) : Flash a bitstream on a FPGA card.
+- [fasm2frames](https://github.com/f4pga/prjxray) : Converts fasm files to frames files.
+- [xc7frames2bit](https://github.com/f4pga/prjxray) : Converts frames files to bitstream.
+- [openFPGALoader](https://github.com/trabucayre/openFPGALoader) : Flashes a bitstream onto an FPGA card.
 
-The image also contains some [databases](https://github.com/f4pga/prjxray-db) needed for prjxray tools to work.
+The image also includes some [databases](https://github.com/f4pga/prjxray-db) required for the prjxray tools to function.
 
 # Usage
 
-See the small [example](./example/).
+See the provided [example](./example/).
diff --git a/example/README.md b/example/README.md
index b229b31..ea8d80a 100644
--- a/example/README.md
+++ b/example/README.md
@@ -1,30 +1,30 @@
 # Example
 
-This directory shows how to flash a system verilog program (A full-adder) on a Zybo `xc7z010clg400-1` card.
+This directory shows how to flash a SystemVerilog program (a full-adder) on a Zybo `xc7z010clg400-1` board.
 
 ## Build
 
-Firstly, the system verilog file needs to be converted to verilog in order to use it with yosys :
+Firstly, the SystemVerilog file needs to be converted to verilog to use it with Yosys :
 
 ```bash
 podman run --mount=type=bind,source=.,target=/root/code fmn_alpine sv2v adder.sv -w adder.v
 ```
 
-The mount parameter is used to provide to podman the current directory.
+The mount parameter is used to provide the current directory to podman.
 
-Then, yosys can achieve the RTL synthesis of the program :
+Then, Yosys can perform the RTL synthesis of the program :
 
 ```bash
 podman run --mount=type=bind,source=.,target=/root/code fmn_alpine yosys adder.v -p "synth_xilinx; write_json synthesis.json"
 ```
 
-Nextpnr can now place and route each components using the xdc constraints file :
+Nextpnr can now place and route each component using the XDC constraints file :
 
 ```bash
 podman run --mount=type=bind,source=.,target=/root/code fmn_alpine nextpnr-himbaechel --json synthesis.json -o xdc=adder.xdc -o fasm=out.fasm --device xc7z010clg400-1
 ```
 
-Now the fasm file can be converted in a frames file and then in a bitstream :
+Now the FASM file can be converted to a frames file and then to a bitstream :
 
 ```bash
 podman run --mount=type=bind,source=.,target=/root/code fmn_alpine fasm2frames --part xc7z010clg400-1 --db-root /usr/share/xray/database/zynq7 out.fasm out.frames
@@ -33,9 +33,9 @@ podman run --mount=type=bind,source=.,target=/root/code fmn_alpine xc7frames2bit
 
 ## Flashing the FPGA
 
-Finally, we can flash the bitstream on the card with `openFPGALoader`.
+Finally, we can flash the bitstream on the board with `openFPGALoader`.
 
-Podman requires a device argument to allow openFPGALoader to access the usb interface. You can find this path with `lsusb` :
+Podman requires a device argument to allow `openFPGALoader` to access the USB interface. You can find this path with `lsusb` :
 
 ```txt
 Bus 003 Device 005: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC