mwa/bisare_sim_rs
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performance improvement

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This commit is contained in:
Mwa
2026-03-20 11:08:18 +01:00
parent c72e133cde
commit ff6427b020
2 changed files with 297 additions and 282 deletions
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47
simu/src/cpu.rs
View File

@@ -396,7 +396,7 @@ impl Computer {
new
}
#[inline(always)]
pub fn step(&mut self) {
pub fn step(&mut self, s: usize) {
match self.interupts {
InteruptState::Disabled => {}
InteruptState::Enabled => {
@@ -415,7 +415,7 @@ impl Computer {
}
InteruptState::Serving(..) => {}
}
for _ in 0..s {
//potentially just changed by interupt.
let next_opcode = self.ram[self.pc];
@@ -541,23 +541,33 @@ impl Computer {
} else {
match addr as isize - 0x0120_0000 {
#[cfg(feature = "rich_keyboard")]
-12 => {
SHARED.keyboard[0].load(std::sync::atomic::Ordering::Relaxed)
}
-12 => SHARED.keyboard[0]
.load(std::sync::atomic::Ordering::Relaxed),
#[cfg(feature = "rich_keyboard")]
-8 => SHARED.keyboard[1].load(std::sync::atomic::Ordering::Relaxed),
-8 => SHARED.keyboard[1]
.load(std::sync::atomic::Ordering::Relaxed),
#[cfg(feature = "rich_keyboard")]
-4 => SHARED.keyboard[2].load(std::sync::atomic::Ordering::Relaxed),
0 => SHARED.keyboard[3].load(std::sync::atomic::Ordering::Relaxed),
-4 => SHARED.keyboard[2]
.load(std::sync::atomic::Ordering::Relaxed),
0 => SHARED.keyboard[3]
.load(std::sync::atomic::Ordering::Relaxed),
4 => time::Instant::now()
.duration_since(self.creation)
.as_millis() as u32,
.as_millis()
as u32,
8 => SHARED.mouse[0].load(std::sync::atomic::Ordering::Relaxed),
12 => SHARED.mouse[1].load(std::sync::atomic::Ordering::Relaxed),
16 => SHARED.mouse[2].load(std::sync::atomic::Ordering::Relaxed),
12 => {
SHARED.mouse[1].load(std::sync::atomic::Ordering::Relaxed)
}
16 => {
SHARED.mouse[2].load(std::sync::atomic::Ordering::Relaxed)
}
//guaranted by the inequality and is multiple of 4
_ => {
self.serve_interupt(InteruptKind::IllegalOpcode, [next_opcode]);
self.serve_interupt(
InteruptKind::IllegalOpcode,
[next_opcode],
);
return;
}
}
@@ -652,7 +662,8 @@ impl Computer {
self.interupts = InteruptState::Enabled
}
InteruptKind::Swi => {}
InteruptKind::DivByZero | InteruptKind::UnsupportedOpcode => {
InteruptKind::DivByZero
| InteruptKind::UnsupportedOpcode => {
ret_index = Some(self.regs[0]);
ret_value = self.regs[1];
}
@@ -691,7 +702,8 @@ impl Computer {
(&SHARED.external_enabled_interupts)
.store(0, std::sync::atomic::Ordering::Relaxed);
(&SHARED.external_interupts).store(0, std::sync::atomic::Ordering::Relaxed);
(&SHARED.external_interupts)
.store(0, std::sync::atomic::Ordering::Relaxed);
SHARED.external_interupts.signal();
}
Instruction::Swi() => {
@@ -716,14 +728,17 @@ impl Computer {
Err((kind, rx, ry, op2, opcode)) => {
self.pc += 1;
match kind {
InteruptKind::UnsupportedOpcode => self
.serve_interupt(kind, [rx.0.into(), self[ry], self.resolve(op2), opcode]),
InteruptKind::UnsupportedOpcode => self.serve_interupt(
kind,
[rx.0.into(), self[ry], self.resolve(op2), opcode],
),
InteruptKind::IllegalOpcode => self.serve_interupt(kind, [next_opcode]),
_ => unsafe { unreachable_unchecked() },
}
}
}
}
}
fn resolve(&self, op2: Op2) -> u32 {
match op2 {
Op2::Direct(v) => v,

10
simu/src/main.rs
View File

@@ -303,7 +303,7 @@ fn main() -> Result<(), Error> {
let mut simulation = Computer::new(program);
#[cfg(not(feature = "debug"))]
loop {
simulation.step();
simulation.step(64);
}
#[cfg(feature = "debug")]
{
@@ -371,13 +371,13 @@ fn main() -> Result<(), Error> {
println!("cannot step, cpu killed");
break;
}
simulation.step();
simulation.step(1);
}
false
}
"r" | "run" => {
while !simulation.error {
simulation.step();
simulation.step(64);
}
false
}
@@ -408,7 +408,7 @@ fn main() -> Result<(), Error> {
while !simulation.error
&& simulation.ram[simulation.pc] != 0x8800_0000
{
simulation.step();
simulation.step(1);
}
false
}
@@ -419,7 +419,7 @@ fn main() -> Result<(), Error> {
while !simulation.error
&& simulation.pc != (v as usize / 4)
{
simulation.step();
simulation.step(1);
}
false
}