performance improvement
This commit is contained in:
569
simu/src/cpu.rs
569
simu/src/cpu.rs
@@ -396,7 +396,7 @@ impl Computer {
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new
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new
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}
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}
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#[inline(always)]
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#[inline(always)]
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pub fn step(&mut self) {
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pub fn step(&mut self, s: usize) {
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match self.interupts {
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match self.interupts {
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InteruptState::Disabled => {}
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InteruptState::Disabled => {}
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InteruptState::Enabled => {
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InteruptState::Enabled => {
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@@ -415,311 +415,326 @@ impl Computer {
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}
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}
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InteruptState::Serving(..) => {}
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InteruptState::Serving(..) => {}
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}
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}
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for _ in 0..s {
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//potentially just changed by interupt.
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let next_opcode = self.ram[self.pc];
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//potentially just changed by interupt.
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let instruction = Instruction::try_from(next_opcode);
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let next_opcode = self.ram[self.pc];
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let instruction = Instruction::try_from(next_opcode);
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match instruction {
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Ok(instruction) => {
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match instruction {
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match instruction {
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Ok(instruction) => {
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Instruction::Copy(reg, op2) => {
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match instruction {
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self[reg] = self.resolve(op2);
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Instruction::Copy(reg, op2) => {
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self.pc += 1;
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self[reg] = self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Add(reg, reg1, op2) => {
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self[reg] = self[reg1] + self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Sub(reg, reg1, op2) => {
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self[reg] = self[reg1] - self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Or(reg, reg1, op2) => {
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self[reg] = self[reg1] | self.resolve(op2);
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self.pc += 1;
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}
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Instruction::And(reg, reg1, op2) => {
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self[reg] = self[reg1] & self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Xor(reg, reg1, op2) => {
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self[reg] = self[reg1] ^ self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Lsl(reg, reg1, op2) => {
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self[reg] = (self[reg1] as u64).wrapping_shl(self.resolve(op2)) as u32;
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self.pc += 1;
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}
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Instruction::Lsr(reg, reg1, op2) => {
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self[reg] = (self[reg1] as u64).wrapping_shr(self.resolve(op2)) as u32;
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self.pc += 1;
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}
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Instruction::Asr(reg, reg1, op2) => {
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self[reg] = (self[reg1] as i64).wrapping_shr(self.resolve(op2)) as u32;
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self.pc += 1;
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}
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Instruction::Umull(reg, reg1, op2) => {
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self[reg] = self[reg1].wrapping_mul(self.resolve(op2));
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self.pc += 1;
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}
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Instruction::Smull(reg, reg1, op2) => {
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self[reg] =
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(self[reg1] as i32).wrapping_mul(self.resolve(op2) as i32) as u32;
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self.pc += 1;
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}
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Instruction::Umulh(reg, reg1, op2) => {
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self[reg] = self[reg1].widening_mul(self.resolve(op2)).1;
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self.pc += 1;
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}
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Instruction::Smulh(reg, reg1, op2) => {
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self[reg] =
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(self[reg1] as i32).widening_mul(self.resolve(op2) as i32).1 as u32;
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self.pc += 1;
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}
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Instruction::Div(reg, reg1, op2) => {
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self.pc += 1;
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let d = self.resolve(op2);
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if unlikely(d == 0) {
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self.serve_interupt(
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InteruptKind::DivByZero,
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[reg.0.into(), self[reg1]],
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);
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return;
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}
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}
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self[reg] = self[reg1] / d;
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Instruction::Add(reg, reg1, op2) => {
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}
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self[reg] = self[reg1] + self.resolve(op2);
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Instruction::Mod(reg, reg1, op2) => {
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self.pc += 1;
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self[reg] = self[reg1] % self.resolve(op2);
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self.pc += 1
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}
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Instruction::Store(reg, op2, reg1) => {
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self.pc += 1;
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let addr = (self[reg].wrapping_add(self.resolve(op2))) as usize;
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if !addr.is_multiple_of(4) {
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self.serve_interupt(
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InteruptKind::IllegalLoadStore,
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[1, addr as u32, self[reg1]],
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);
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return;
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}
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}
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if addr <= 0x00ffffff {
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Instruction::Sub(reg, reg1, op2) => {
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self.ram[addr / 4] = self[reg1];
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self[reg] = self[reg1] - self.resolve(op2);
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} else if addr <= 0x00ff_ffff + 480 * 640 * 4 {
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self.pc += 1;
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let buf_addr = (addr - 0x0100_0000) / 4;
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let dat = if cfg!(feature = "rgba") {
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self[reg1]
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} else {
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self[reg1] & 0x00FF_FFFF
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};
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(&SHARED.screen_buf[buf_addr])
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.store(dat, std::sync::atomic::Ordering::Relaxed);
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} else if addr == 0x0120_1000 {
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(&SHARED.external_enabled_interupts)
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.store(self[reg1], std::sync::atomic::Ordering::Relaxed);
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} else {
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self.serve_interupt(InteruptKind::IllegalOpcode, [next_opcode]);
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}
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}
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}
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Instruction::Or(reg, reg1, op2) => {
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Instruction::Load(reg, reg1, op2) => {
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self[reg] = self[reg1] | self.resolve(op2);
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self.pc += 1;
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self.pc += 1;
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let addr = (self[reg1].wrapping_add(self.resolve(op2))) as usize;
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if !addr.is_multiple_of(4) {
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self.serve_interupt(
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InteruptKind::IllegalLoadStore,
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[0, addr as u32, reg.0 as u32],
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);
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return;
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}
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}
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self[reg] = if addr <= 0x00ffffff {
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Instruction::And(reg, reg1, op2) => {
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self.ram[addr / 4]
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self[reg] = self[reg1] & self.resolve(op2);
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} else if addr <= 0x00ffffff + 480 * 640 * 4 {
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self.pc += 1;
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let buf_addr = (addr - 0x0100_0000) / 4;
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}
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(&SHARED.screen_buf[buf_addr])
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Instruction::Xor(reg, reg1, op2) => {
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.load(std::sync::atomic::Ordering::Relaxed)
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self[reg] = self[reg1] ^ self.resolve(op2);
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} else {
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self.pc += 1;
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match addr as isize - 0x0120_0000 {
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}
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#[cfg(feature = "rich_keyboard")]
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Instruction::Lsl(reg, reg1, op2) => {
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-12 => {
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self[reg] = (self[reg1] as u64).wrapping_shl(self.resolve(op2)) as u32;
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SHARED.keyboard[0].load(std::sync::atomic::Ordering::Relaxed)
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self.pc += 1;
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}
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}
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#[cfg(feature = "rich_keyboard")]
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Instruction::Lsr(reg, reg1, op2) => {
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-8 => SHARED.keyboard[1].load(std::sync::atomic::Ordering::Relaxed),
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self[reg] = (self[reg1] as u64).wrapping_shr(self.resolve(op2)) as u32;
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#[cfg(feature = "rich_keyboard")]
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self.pc += 1;
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-4 => SHARED.keyboard[2].load(std::sync::atomic::Ordering::Relaxed),
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}
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0 => SHARED.keyboard[3].load(std::sync::atomic::Ordering::Relaxed),
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Instruction::Asr(reg, reg1, op2) => {
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4 => time::Instant::now()
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self[reg] = (self[reg1] as i64).wrapping_shr(self.resolve(op2)) as u32;
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.duration_since(self.creation)
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self.pc += 1;
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.as_millis() as u32,
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}
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8 => SHARED.mouse[0].load(std::sync::atomic::Ordering::Relaxed),
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Instruction::Umull(reg, reg1, op2) => {
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12 => SHARED.mouse[1].load(std::sync::atomic::Ordering::Relaxed),
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self[reg] = self[reg1].wrapping_mul(self.resolve(op2));
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16 => SHARED.mouse[2].load(std::sync::atomic::Ordering::Relaxed),
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self.pc += 1;
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//guaranted by the inequality and is multiple of 4
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}
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_ => {
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Instruction::Smull(reg, reg1, op2) => {
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self.serve_interupt(InteruptKind::IllegalOpcode, [next_opcode]);
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self[reg] =
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return;
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(self[reg1] as i32).wrapping_mul(self.resolve(op2) as i32) as u32;
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}
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self.pc += 1;
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}
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Instruction::Umulh(reg, reg1, op2) => {
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self[reg] = self[reg1].widening_mul(self.resolve(op2)).1;
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self.pc += 1;
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}
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Instruction::Smulh(reg, reg1, op2) => {
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self[reg] =
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(self[reg1] as i32).widening_mul(self.resolve(op2) as i32).1 as u32;
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self.pc += 1;
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}
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Instruction::Div(reg, reg1, op2) => {
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self.pc += 1;
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let d = self.resolve(op2);
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if unlikely(d == 0) {
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self.serve_interupt(
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InteruptKind::DivByZero,
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[reg.0.into(), self[reg1]],
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);
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return;
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}
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}
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};
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self[reg] = self[reg1] / d;
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}
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Instruction::Push(op2) => {
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self.sp -= 1;
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self.ram[self.sp] = self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Pop(reg) => {
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self[reg] = self.ram[self.sp];
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self.sp += 1;
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self.pc += 1;
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}
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Instruction::Skip(d, cond, reg, op2) => {
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self.pc += 1;
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if cond.eval(self[reg], self.resolve(op2)) {
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self.pc += d as usize
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}
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}
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}
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Instruction::Mod(reg, reg1, op2) => {
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Instruction::Jump(mut addr) => {
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self[reg] = self[reg1] % self.resolve(op2);
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if addr & (1 << 28) != 0 {
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self.pc += 1
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addr += 7 << 29;
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}
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} else if addr == 0 {
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Instruction::Store(reg, op2, reg1) => {
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#[cfg(feature = "debug")]
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self.pc += 1;
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{
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let addr = (self[reg].wrapping_add(self.resolve(op2))) as usize;
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match self.interupts {
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if !addr.is_multiple_of(4) {
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InteruptState::Disabled => {
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self.serve_interupt(
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println!("program terminated");
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InteruptKind::IllegalLoadStore,
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[1, addr as u32, self[reg1]],
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);
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return;
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}
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if addr <= 0x00ffffff {
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self.ram[addr / 4] = self[reg1];
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} else if addr <= 0x00ff_ffff + 480 * 640 * 4 {
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let buf_addr = (addr - 0x0100_0000) / 4;
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let dat = if cfg!(feature = "rgba") {
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self[reg1]
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} else {
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self[reg1] & 0x00FF_FFFF
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};
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(&SHARED.screen_buf[buf_addr])
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.store(dat, std::sync::atomic::Ordering::Relaxed);
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} else if addr == 0x0120_1000 {
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(&SHARED.external_enabled_interupts)
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.store(self[reg1], std::sync::atomic::Ordering::Relaxed);
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} else {
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self.serve_interupt(InteruptKind::IllegalOpcode, [next_opcode]);
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}
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}
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Instruction::Load(reg, reg1, op2) => {
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self.pc += 1;
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let addr = (self[reg1].wrapping_add(self.resolve(op2))) as usize;
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if !addr.is_multiple_of(4) {
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self.serve_interupt(
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InteruptKind::IllegalLoadStore,
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[0, addr as u32, reg.0 as u32],
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);
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return;
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}
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self[reg] = if addr <= 0x00ffffff {
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self.ram[addr / 4]
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} else if addr <= 0x00ffffff + 480 * 640 * 4 {
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let buf_addr = (addr - 0x0100_0000) / 4;
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(&SHARED.screen_buf[buf_addr])
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.load(std::sync::atomic::Ordering::Relaxed)
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} else {
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match addr as isize - 0x0120_0000 {
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#[cfg(feature = "rich_keyboard")]
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-12 => SHARED.keyboard[0]
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.load(std::sync::atomic::Ordering::Relaxed),
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#[cfg(feature = "rich_keyboard")]
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-8 => SHARED.keyboard[1]
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.load(std::sync::atomic::Ordering::Relaxed),
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#[cfg(feature = "rich_keyboard")]
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-4 => SHARED.keyboard[2]
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.load(std::sync::atomic::Ordering::Relaxed),
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0 => SHARED.keyboard[3]
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.load(std::sync::atomic::Ordering::Relaxed),
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4 => time::Instant::now()
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.duration_since(self.creation)
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.as_millis()
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as u32,
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8 => SHARED.mouse[0].load(std::sync::atomic::Ordering::Relaxed),
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12 => {
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SHARED.mouse[1].load(std::sync::atomic::Ordering::Relaxed)
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}
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16 => {
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SHARED.mouse[2].load(std::sync::atomic::Ordering::Relaxed)
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}
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//guaranted by the inequality and is multiple of 4
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_ => {
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self.serve_interupt(
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InteruptKind::IllegalOpcode,
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[next_opcode],
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);
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return;
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}
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}
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};
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}
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Instruction::Push(op2) => {
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self.sp -= 1;
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self.ram[self.sp] = self.resolve(op2);
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self.pc += 1;
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}
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Instruction::Pop(reg) => {
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self[reg] = self.ram[self.sp];
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self.sp += 1;
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self.pc += 1;
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}
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Instruction::Skip(d, cond, reg, op2) => {
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self.pc += 1;
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if cond.eval(self[reg], self.resolve(op2)) {
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self.pc += d as usize
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}
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}
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Instruction::Jump(mut addr) => {
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if addr & (1 << 28) != 0 {
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addr += 7 << 29;
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} else if addr == 0 {
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#[cfg(feature = "debug")]
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{
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match self.interupts {
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InteruptState::Disabled => {
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|
println!("program terminated");
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self.error = true;
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|
return;
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}
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_ => (),
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}
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if SHARED
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.external_enabled_interupts
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|
.load(std::sync::atomic::Ordering::Relaxed)
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== 0
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{
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|
println!("Program terminated");
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self.error = true;
|
self.error = true;
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return;
|
return;
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}
|
}
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_ => (),
|
println!("awaiting interupt...");
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}
|
}
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if SHARED
|
SHARED.external_interupts.wait(0);
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.external_enabled_interupts
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}
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.load(std::sync::atomic::Ordering::Relaxed)
|
self.pc = (addr + self.pc as u32) as usize;
|
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== 0
|
}
|
||||||
|
Instruction::Call(mut addr) => {
|
||||||
|
self.sp -= 1;
|
||||||
|
self.ram[self.sp] = ((self.pc << 2) + 4) as u32;
|
||||||
|
|
||||||
|
if addr & (1 << 28) != 0 {
|
||||||
|
addr += 7 << 29;
|
||||||
|
} else if unlikely(addr == 0) {
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
{
|
{
|
||||||
println!("Program terminated");
|
println!("program terminated");
|
||||||
self.error = true;
|
self.error = true;
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
println!("awaiting interupt...");
|
#[cfg(not(feature = "debug"))]
|
||||||
|
exit(0);
|
||||||
}
|
}
|
||||||
SHARED.external_interupts.wait(0);
|
self.pc = (addr + self.pc as u32) as usize;
|
||||||
}
|
}
|
||||||
self.pc = (addr + self.pc as u32) as usize;
|
Instruction::Ret() => {
|
||||||
}
|
self.pc = (self.ram[self.sp] >> 2) as usize;
|
||||||
Instruction::Call(mut addr) => {
|
self.sp += 1;
|
||||||
self.sp -= 1;
|
|
||||||
self.ram[self.sp] = ((self.pc << 2) + 4) as u32;
|
|
||||||
|
|
||||||
if addr & (1 << 28) != 0 {
|
|
||||||
addr += 7 << 29;
|
|
||||||
} else if unlikely(addr == 0) {
|
|
||||||
#[cfg(feature = "debug")]
|
|
||||||
{
|
|
||||||
println!("program terminated");
|
|
||||||
self.error = true;
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
#[cfg(not(feature = "debug"))]
|
|
||||||
exit(0);
|
|
||||||
}
|
}
|
||||||
self.pc = (addr + self.pc as u32) as usize;
|
Instruction::Reti() => {
|
||||||
}
|
let mut ret_index = None;
|
||||||
Instruction::Ret() => {
|
let mut ret_value = 0;
|
||||||
self.pc = (self.ram[self.sp] >> 2) as usize;
|
|
||||||
self.sp += 1;
|
|
||||||
}
|
|
||||||
Instruction::Reti() => {
|
|
||||||
let mut ret_index = None;
|
|
||||||
let mut ret_value = 0;
|
|
||||||
|
|
||||||
match self.interupts {
|
match self.interupts {
|
||||||
InteruptState::Serving(kind, prev) => {
|
InteruptState::Serving(kind, prev) => {
|
||||||
match prev.highest_one() {
|
match prev.highest_one() {
|
||||||
None => self.interupts = InteruptState::Enabled,
|
None => self.interupts = InteruptState::Enabled,
|
||||||
Some(i) => {
|
Some(i) => {
|
||||||
self.interupts =
|
self.interupts =
|
||||||
InteruptState::Serving(i.into(), prev ^ (1 << i))
|
InteruptState::Serving(i.into(), prev ^ (1 << i))
|
||||||
}
|
|
||||||
}
|
|
||||||
match kind {
|
|
||||||
InteruptKind::MMIO => {
|
|
||||||
(&SHARED.external_interupts)
|
|
||||||
.store(0, std::sync::atomic::Ordering::Release);
|
|
||||||
SHARED.external_interupts.signal();
|
|
||||||
//no need to check prev because MMIO is the lowest priority
|
|
||||||
self.interupts = InteruptState::Enabled
|
|
||||||
}
|
|
||||||
InteruptKind::Swi => {}
|
|
||||||
InteruptKind::DivByZero | InteruptKind::UnsupportedOpcode => {
|
|
||||||
ret_index = Some(self.regs[0]);
|
|
||||||
ret_value = self.regs[1];
|
|
||||||
}
|
|
||||||
InteruptKind::IllegalLoadStore => {
|
|
||||||
if self.regs[0] == 0 {
|
|
||||||
ret_value = self.regs[1];
|
|
||||||
ret_index = Some(self.regs[2]);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
InteruptKind::IllegalOpcode => {}
|
match kind {
|
||||||
|
InteruptKind::MMIO => {
|
||||||
|
(&SHARED.external_interupts)
|
||||||
|
.store(0, std::sync::atomic::Ordering::Release);
|
||||||
|
SHARED.external_interupts.signal();
|
||||||
|
//no need to check prev because MMIO is the lowest priority
|
||||||
|
self.interupts = InteruptState::Enabled
|
||||||
|
}
|
||||||
|
InteruptKind::Swi => {}
|
||||||
|
InteruptKind::DivByZero
|
||||||
|
| InteruptKind::UnsupportedOpcode => {
|
||||||
|
ret_index = Some(self.regs[0]);
|
||||||
|
ret_value = self.regs[1];
|
||||||
|
}
|
||||||
|
InteruptKind::IllegalLoadStore => {
|
||||||
|
if self.regs[0] == 0 {
|
||||||
|
ret_value = self.regs[1];
|
||||||
|
ret_index = Some(self.regs[2]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
InteruptKind::IllegalOpcode => {}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
_ => { /* This is a troubling case but ... well it's ok */ }
|
||||||
|
}
|
||||||
|
let ret = self.ram[self.sp];
|
||||||
|
self.pc = (ret & 0x0FFF_FFFF) as usize;
|
||||||
|
self.sp += 1 as usize;
|
||||||
|
for i in (0..(ret >> 28) as usize).rev() {
|
||||||
|
self.regs[i] = self.ram[self.sp];
|
||||||
|
self.sp += 1
|
||||||
|
}
|
||||||
|
if let Some(idx) = ret_index {
|
||||||
|
self.regs[idx as usize] = ret_value;
|
||||||
}
|
}
|
||||||
_ => { /* This is a troubling case but ... well it's ok */ }
|
|
||||||
}
|
}
|
||||||
let ret = self.ram[self.sp];
|
Instruction::Eint() => {
|
||||||
self.pc = (ret & 0x0FFF_FFFF) as usize;
|
match self.interupts {
|
||||||
self.sp += 1 as usize;
|
InteruptState::Disabled => self.interupts = InteruptState::Enabled,
|
||||||
for i in (0..(ret >> 28) as usize).rev() {
|
_ => {}
|
||||||
self.regs[i] = self.ram[self.sp];
|
}
|
||||||
self.sp += 1
|
self.pc += 1;
|
||||||
}
|
}
|
||||||
if let Some(idx) = ret_index {
|
Instruction::Dint() => {
|
||||||
self.regs[idx as usize] = ret_value;
|
self.interupts = InteruptState::Disabled;
|
||||||
}
|
self.pc += 1;
|
||||||
}
|
|
||||||
Instruction::Eint() => {
|
|
||||||
match self.interupts {
|
|
||||||
InteruptState::Disabled => self.interupts = InteruptState::Enabled,
|
|
||||||
_ => {}
|
|
||||||
}
|
|
||||||
self.pc += 1;
|
|
||||||
}
|
|
||||||
Instruction::Dint() => {
|
|
||||||
self.interupts = InteruptState::Disabled;
|
|
||||||
self.pc += 1;
|
|
||||||
|
|
||||||
(&SHARED.external_enabled_interupts)
|
(&SHARED.external_enabled_interupts)
|
||||||
.store(0, std::sync::atomic::Ordering::Relaxed);
|
.store(0, std::sync::atomic::Ordering::Relaxed);
|
||||||
(&SHARED.external_interupts).store(0, std::sync::atomic::Ordering::Relaxed);
|
(&SHARED.external_interupts)
|
||||||
SHARED.external_interupts.signal();
|
.store(0, std::sync::atomic::Ordering::Relaxed);
|
||||||
}
|
SHARED.external_interupts.signal();
|
||||||
Instruction::Swi() => {
|
|
||||||
self.pc += 1;
|
|
||||||
self.serve_interupt(InteruptKind::Swi, []);
|
|
||||||
}
|
|
||||||
Instruction::GetStack(reg) => {
|
|
||||||
self[reg] = (self.sp << 2) as u32;
|
|
||||||
self.pc += 1;
|
|
||||||
}
|
|
||||||
Instruction::SetStack(op2) => {
|
|
||||||
let v = self.resolve(op2);
|
|
||||||
if likely(v.is_multiple_of(4)) {
|
|
||||||
self.sp = (v >> 2) as usize;
|
|
||||||
} else {
|
|
||||||
self.sp = usize::MAX //Yes, that means that clever program using sp to store information wont work on my emulator. Deal with it
|
|
||||||
}
|
}
|
||||||
self.pc += 1;
|
Instruction::Swi() => {
|
||||||
|
self.pc += 1;
|
||||||
|
self.serve_interupt(InteruptKind::Swi, []);
|
||||||
|
}
|
||||||
|
Instruction::GetStack(reg) => {
|
||||||
|
self[reg] = (self.sp << 2) as u32;
|
||||||
|
self.pc += 1;
|
||||||
|
}
|
||||||
|
Instruction::SetStack(op2) => {
|
||||||
|
let v = self.resolve(op2);
|
||||||
|
if likely(v.is_multiple_of(4)) {
|
||||||
|
self.sp = (v >> 2) as usize;
|
||||||
|
} else {
|
||||||
|
self.sp = usize::MAX //Yes, that means that clever program using sp to store information wont work on my emulator. Deal with it
|
||||||
|
}
|
||||||
|
self.pc += 1;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
}
|
||||||
|
Err((kind, rx, ry, op2, opcode)) => {
|
||||||
|
self.pc += 1;
|
||||||
|
match kind {
|
||||||
|
InteruptKind::UnsupportedOpcode => self.serve_interupt(
|
||||||
|
kind,
|
||||||
|
[rx.0.into(), self[ry], self.resolve(op2), opcode],
|
||||||
|
),
|
||||||
|
InteruptKind::IllegalOpcode => self.serve_interupt(kind, [next_opcode]),
|
||||||
|
_ => unsafe { unreachable_unchecked() },
|
||||||
}
|
}
|
||||||
};
|
|
||||||
}
|
|
||||||
Err((kind, rx, ry, op2, opcode)) => {
|
|
||||||
self.pc += 1;
|
|
||||||
match kind {
|
|
||||||
InteruptKind::UnsupportedOpcode => self
|
|
||||||
.serve_interupt(kind, [rx.0.into(), self[ry], self.resolve(op2), opcode]),
|
|
||||||
InteruptKind::IllegalOpcode => self.serve_interupt(kind, [next_opcode]),
|
|
||||||
_ => unsafe { unreachable_unchecked() },
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -303,7 +303,7 @@ fn main() -> Result<(), Error> {
|
|||||||
let mut simulation = Computer::new(program);
|
let mut simulation = Computer::new(program);
|
||||||
#[cfg(not(feature = "debug"))]
|
#[cfg(not(feature = "debug"))]
|
||||||
loop {
|
loop {
|
||||||
simulation.step();
|
simulation.step(64);
|
||||||
}
|
}
|
||||||
#[cfg(feature = "debug")]
|
#[cfg(feature = "debug")]
|
||||||
{
|
{
|
||||||
@@ -371,13 +371,13 @@ fn main() -> Result<(), Error> {
|
|||||||
println!("cannot step, cpu killed");
|
println!("cannot step, cpu killed");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
simulation.step();
|
simulation.step(1);
|
||||||
}
|
}
|
||||||
false
|
false
|
||||||
}
|
}
|
||||||
"r" | "run" => {
|
"r" | "run" => {
|
||||||
while !simulation.error {
|
while !simulation.error {
|
||||||
simulation.step();
|
simulation.step(64);
|
||||||
}
|
}
|
||||||
false
|
false
|
||||||
}
|
}
|
||||||
@@ -408,7 +408,7 @@ fn main() -> Result<(), Error> {
|
|||||||
while !simulation.error
|
while !simulation.error
|
||||||
&& simulation.ram[simulation.pc] != 0x8800_0000
|
&& simulation.ram[simulation.pc] != 0x8800_0000
|
||||||
{
|
{
|
||||||
simulation.step();
|
simulation.step(1);
|
||||||
}
|
}
|
||||||
false
|
false
|
||||||
}
|
}
|
||||||
@@ -419,7 +419,7 @@ fn main() -> Result<(), Error> {
|
|||||||
while !simulation.error
|
while !simulation.error
|
||||||
&& simulation.pc != (v as usize / 4)
|
&& simulation.pc != (v as usize / 4)
|
||||||
{
|
{
|
||||||
simulation.step();
|
simulation.step(1);
|
||||||
}
|
}
|
||||||
false
|
false
|
||||||
}
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user