mwa/bisare_sim_rs
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specifyng wrapping add

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Mwa
2026-03-12 15:10:14 +01:00
parent 2741332630
commit d762e1449b
2 changed files with 7 additions and 5 deletions
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2
asm/src/main.rs
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@@ -309,7 +309,7 @@ fn op2(s: &str, n: usize, l: &str) -> Op2 {
"r15" => 15, "r15" => 15,
_ => match parse_int::parse::<i64>(s) { _ => match parse_int::parse::<i64>(s) {
Ok(v) => { Ok(v) => {
if -0xFFFF <= v && v <= 0xFFFF { if -0x10000 <= v && v <= 0xFFFF {
return Op2::Direct(v as i32); return Op2::Direct(v as i32);
} else { } else {
println!("Error: constant {s} is too large to fit in {l} at line {n}"); println!("Error: constant {s} is too large to fit in {l} at line {n}");

8
simu/src/cpu.rs
View File

@@ -266,7 +266,7 @@ impl<'a, 'b> Computer<'a, 'b> {
self.pc += 1 self.pc += 1
} }
Instruction::Store(reg, op2, reg1) => { Instruction::Store(reg, op2, reg1) => {
let addr = (self.rg_r(reg) + self.resolve(op2)) as usize; let addr = (self.rg_r(reg).wrapping_add(self.resolve(op2))) as usize;
if !addr.is_multiple_of(4) { if !addr.is_multiple_of(4) {
iot(); iot();
} }
@@ -287,7 +287,7 @@ impl<'a, 'b> Computer<'a, 'b> {
self.pc += 1; self.pc += 1;
} }
Instruction::Load(reg, reg1, op2) => { Instruction::Load(reg, reg1, op2) => {
let addr = (self.rg_r(reg1) + self.resolve(op2)) as usize; let addr = (self.rg_r(reg1).wrapping_add(self.resolve(op2))) as usize;
if !addr.is_multiple_of(4) { if !addr.is_multiple_of(4) {
iot(); iot();
} }
@@ -307,7 +307,9 @@ impl<'a, 'b> Computer<'a, 'b> {
} else if addr == 0x01200000 { } else if addr == 0x01200000 {
self.key.load(std::sync::atomic::Ordering::Relaxed) self.key.load(std::sync::atomic::Ordering::Relaxed)
} else if addr == 0x01200004 { } else if addr == 0x01200004 {
time::Instant::now().duration_since(self.creation).as_millis() as u32 time::Instant::now()
.duration_since(self.creation)
.as_millis() as u32
} else { } else {
iot(); iot();
}, },