mwa/bisare_sim_rs
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specifyng wrapping add

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Mwa
2026-03-12 15:10:14 +01:00
parent 2741332630
commit d762e1449b
2 changed files with 7 additions and 5 deletions
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10
simu/src/cpu.rs
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@@ -266,7 +266,7 @@ impl<'a, 'b> Computer<'a, 'b> {
self.pc += 1
}
Instruction::Store(reg, op2, reg1) => {
let addr = (self.rg_r(reg) + self.resolve(op2)) as usize;
let addr = (self.rg_r(reg).wrapping_add(self.resolve(op2))) as usize;
if !addr.is_multiple_of(4) {
iot();
}
@@ -287,7 +287,7 @@ impl<'a, 'b> Computer<'a, 'b> {
self.pc += 1;
}
Instruction::Load(reg, reg1, op2) => {
let addr = (self.rg_r(reg1) + self.resolve(op2)) as usize;
let addr = (self.rg_r(reg1).wrapping_add(self.resolve(op2))) as usize;
if !addr.is_multiple_of(4) {
iot();
}
@@ -306,8 +306,10 @@ impl<'a, 'b> Computer<'a, 'b> {
res
} else if addr == 0x01200000 {
self.key.load(std::sync::atomic::Ordering::Relaxed)
} else if addr == 0x01200004{
time::Instant::now().duration_since(self.creation).as_millis() as u32
} else if addr == 0x01200004 {
time::Instant::now()
.duration_since(self.creation)
.as_millis() as u32
} else {
iot();
},