mwa/bisare_sim_rs
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minor bugfixes

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This commit is contained in:
Mwa
2026-03-16 18:10:43 +01:00
parent 636ff0a430
commit cd2e5319bc
3 changed files with 12 additions and 3 deletions
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8
simu/src/main.rs
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@@ -323,7 +323,11 @@ fn main() -> Result<(), Error> {
simulation.regs[i + 1]
);
}
println!("SP: {:08x} PC: {:08x}", simulation.sp, simulation.pc);
println!(
"SP: {:08x} PC: {:08x}",
simulation.sp * 4,
simulation.pc * 4
);
println!("RAM near SP");
let min_pc = (simulation.pc).min(0x0100_0000 / 4 - 8);
let min_sp = (simulation.sp).min(0x0100_0000 / 4 - 8);
@@ -381,7 +385,7 @@ fn main() -> Result<(), Error> {
if next.len() >= 2 {
match parse_int::parse::<u32>(next[1]) {
Ok(i) => {
let v = simulation.ram[i as usize/4];
let v = simulation.ram[i as usize / 4];
println!(
"0x{:8x} -- {}",
v,