mwa/bisare_sim_rs
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

improved debuger

Browse Source
This commit is contained in:
Mwa
2026-03-16 19:02:00 +01:00
parent 410c54c2f8
commit a43277c159
1 changed files with 6 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
simu/src/main.rs
View File

@@ -416,15 +416,17 @@ fn main() -> Result<(), Error> {
if next.len() >= 2 { if next.len() >= 2 {
match parse_int::parse::<u32>(next[1]) { match parse_int::parse::<u32>(next[1]) {
Ok(v) => { Ok(v) => {
while !simulation.error && simulation.pc != (v as usize/4) { while !simulation.error
&& simulation.pc != (v as usize / 4)
{
simulation.step(); simulation.step();
} }
false false
}, }
Err(e) => { Err(e) => {
println!("{e}"); println!("{e}");
true true
}, }
} }
} else { } else {
println!("{HELP_MSG}"); println!("{HELP_MSG}");
@@ -464,4 +466,5 @@ run - run program until exit / error (alias r)
context - print context (alias c) context - print context (alias c)
print n - print ram content at address n and next 8 (alias p) print n - print ram content at address n and next 8 (alias p)
up - run until the nex ret is reached (alias u) up - run until the nex ret is reached (alias u)
to n - tun until PC = n (alias t)
"; ";