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fixed up debug PC/SP addr

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Mwa
2026-03-26 20:26:51 +01:00
parent e97b4c4ee4
commit 96c3a514f2
1 changed files with 1 additions and 1 deletions
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2
simu/src/main.rs
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@@ -505,7 +505,7 @@ fn debug_context(com: &Computer) {
com.regs[i + 8] com.regs[i + 8]
); );
} }
println!("SP={:08x} PC={:08x}", com.sp, com.pc); println!("SP={:08x} PC={:08x}", com.sp * 4, com.pc * 4);
println!("RAM at SP | Ram at PC:"); println!("RAM at SP | Ram at PC:");
let mut pc_lines = Vec::new(); let mut pc_lines = Vec::new();