mwa/bisare_sim_rs
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Explained and finalized interrupts

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This commit is contained in:
Mwa
2026-03-16 00:40:53 +01:00
parent c38bb22e88
commit 8cb41c61cd
2 changed files with 97 additions and 22 deletions
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34
simu/src/cpu.rs
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@@ -214,7 +214,9 @@ impl TryFrom<u32> for Instruction {
| (1, 0b1011)
| (1, 0b1100)
| (1, 0b1101)
| (1, 0b1110) => return Err((InteruptKind::UnsupportedOpcode, rd, rx, op2)),
| (1, 0b1110) => {
return Err((InteruptKind::UnsupportedOpcode, rd, rx, op2, opcode));
}
(2, 0b0000) => Self::Store(rx, op2, rd),
(2, 0b0001) => Self::Load(rd, rx, op2),
(2, 0b0010) => Self::Push(op2),
@@ -232,13 +234,13 @@ impl TryFrom<u32> for Instruction {
(2, 0b1101) => Self::GetStack(rd),
(2, 0b1110) => Self::SetStack(op2),
(3, skip) => Self::Skip(rd.0, (skip as u8).into(), rx, op2),
_ => return Err((InteruptKind::IllegalOpcode, rd, rx, op2)),
_ => return Err((InteruptKind::IllegalOpcode, rd, rx, op2, opcode)),
}
}
})
}
type Error = (InteruptKind, Reg, Reg, Op2);
type Error = (InteruptKind, Reg, Reg, Op2, u32);
}
pub struct Computer {
@@ -396,7 +398,7 @@ impl Computer {
if !addr.is_multiple_of(4) {
self.serve_interupt(
InteruptKind::IllegalLoadStore,
[0, addr as u32, self[reg1]],
[1, addr as u32, self[reg1]],
);
return;
}
@@ -411,10 +413,7 @@ impl Computer {
(&SHARED.external_enabled_interupts)
.store(self[reg1], std::sync::atomic::Ordering::Relaxed);
} else {
self.serve_interupt(
InteruptKind::IllegalLoadStore,
[0, addr as u32, self[reg1]],
);
self.serve_interupt(InteruptKind::IllegalOpcode, [next_opcode]);
}
}
Instruction::Load(reg, reg1, op2) => {
@@ -446,10 +445,7 @@ impl Computer {
_ => unsafe { unreachable_unchecked() },
}
} else {
self.serve_interupt(
InteruptKind::IllegalLoadStore,
[1, addr as u32, reg.0 as u32],
);
self.serve_interupt(InteruptKind::IllegalOpcode, [next_opcode]);
return;
};
}
@@ -520,7 +516,12 @@ impl Computer {
ret_index = Some(self.regs[0]);
ret_value = self.regs[1];
}
InteruptKind::IllegalLoadStore => {}
InteruptKind::IllegalLoadStore => {
if self.regs[0] == 0 {
ret_value = self.regs[1];
ret_index = Some(self.regs[2]);
}
}
InteruptKind::IllegalOpcode => {}
}
}
@@ -573,12 +574,11 @@ impl Computer {
}
};
}
Err((kind, rx, ry, op2)) => {
Err((kind, rx, ry, op2, opcode)) => {
self.pc += 1;
match kind {
InteruptKind::UnsupportedOpcode => {
self.serve_interupt(kind, [rx.0.into(), self[ry], self.resolve(op2)])
}
InteruptKind::UnsupportedOpcode => self
.serve_interupt(kind, [rx.0.into(), self[ry], self.resolve(op2), opcode]),
InteruptKind::IllegalOpcode => self.serve_interupt(kind, [next_opcode]),
_ => unsafe { unreachable_unchecked() },
}