mwa/bisare_sim_rs
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removed debug print

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Mwa
2026-03-16 19:08:02 +01:00
parent a43277c159
commit 56fcfb5230
1 changed files with 0 additions and 2 deletions
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2
simu/src/cpu.rs
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@@ -388,7 +388,6 @@ impl Computer {
while let Some((_, line)) = lines.next() { while let Some((_, line)) = lines.next() {
if let Some([addr, s]) = line.split_ascii_whitespace().collect::<Vec<_>>().as_array() { if let Some([addr, s]) = line.split_ascii_whitespace().collect::<Vec<_>>().as_array() {
if let Ok(i) = u32::from_str_radix(addr, 16) { if let Ok(i) = u32::from_str_radix(addr, 16) {
println!("adding label {s} at addr {i}");
new.book.insert(i, s.to_string()); new.book.insert(i, s.to_string());
} }
} }
@@ -663,7 +662,6 @@ impl Computer {
} }
_ => { /* This is a troubling case but ... well it's ok */ } _ => { /* This is a troubling case but ... well it's ok */ }
} }
println!("returning from interupt");
let ret = self.ram[self.sp]; let ret = self.ram[self.sp];
self.pc = (ret & 0x0FFF_FFFF) as usize; self.pc = (ret & 0x0FFF_FFFF) as usize;
self.sp += 1 as usize; self.sp += 1 as usize;